• Environmental Engineering Research
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• v.21 no.4
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• pp.409-419
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• 2016

As a major energy consumption province, the issue about the carbon emissions in Hebei Province, China has been concerned by the government. The carbon emissions can be effectively reduced due to a more rational energy consumption structure. Thus, in this paper the constraint of low carbon emissions is considered as a foundation and four energies--coal, petroleum, natural gas and electricity including wind power, nuclear power and hydro-power etc are selected as the main analysis objects of the adjustment of energy structure. This paper takes energy cost minimum and carbon trading cost minimum as the objective functions based on the economic growth, energy saving and emission reduction targets and constructs an optimization model of energy consumption structure. And empirical research about energy consumption structure optimization in 2015 and 2020 is carried out based on the energy consumption data in Hebei Province, China during the period 1995-2013, which indicates that the energy consumption in Hebei dominated by coal cannot be replaced in the next seven years, from 2014 to 2020, when the coal consumption proportion is still up to 85.93%. Finally, the corresponding policy suggestions are put forward, according to the results of the energy structure optimization in Hebei Province.

• Journal of Sensor Science and Technology
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• v.27 no.1
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• pp.59-63
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• 2018

Among Internet of things (IoT) applications, the most demanding requirements for the widespread realization of many IoT visions are security and low power. In terms of security, IoT applications include tasks that are rarely addressed before such as secure computation, trusted sensing, and communication, privacy, and so on. These tasks ask for new and better techniques for the protection of data, software, and hardware. An integral part of hardware cryptographic primitives are secret keys and unique IDs. Physical Unclonable Functions(PUF) are a unique class of circuits that leverage the inherent variations in manufacturing process to create unique, unclonable IDs and secret keys. In this paper, we propose a low power Arbiter PUF circuit with low error rate and high reliability compared with conventional arbiter PUFs. The proposed PUF utilizes a power gating structure to save the power consumption in sleep mode, and uses a razor flip-flop to increase reliability. PUF has been designed and implemented using a FPGA and a ASIC chip (a 0.35 um technology). Experimental results show that our proposed PUF solves the metastability problem and reduce the power consumption of PUF compared to the conventional Arbiter PUF. It is expected that the proposed PUF can be used in systems required low power consumption and high reliability such as low power encryption processors and low power biomedical systems.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.159-163
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• 2004

We have introduced fourth generation PDPs last year. The performance of these PDPs is the highest level among TV displays. At the same time the power consumption of them has reached to the lowest level among FPDs (Flat Panel Displays). High panel luminous efficacy and low address power are necessary for the reduction of total power consumption. Following technologies have been developed and applied to the fourth generation PDPs. High panel luminous efficacy: T-shape electrode, waffle rib structure, high Xe content gas Low address power; CLEAR driving method, etc.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.147-150
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• 2007

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to VDD-2VTH. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we proposed a low-power 16$\times$16 bit parallel multiplier. The proposed circuits are designed with Samsung 0.35$\mu$m standard CMOS process at a 3.3V supply voltage. The validity and effectiveness are verified through the HSPICE simulation.. Compared to the previous works, this circuit can reduce the power consumption rate of 17.3% and the power-delay product of 16.5%.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.1
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• pp.1-6
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• 2014

In this paper, we propose a CPLD low power algorithm considering the structure. The proposed algorithm is implemented CPLD circuit FC(Feasible Cluster) for generating a problem occurs when the node being split to overcome the area and power consumption can reduce the algorithm. CPLD to configure and limitations of the LE is that the number of OR-terms. FC consists of an OR node is divided into mainly as a way to reduce the power consumption with the highest number of output nodes is divided into a top priority. The highest number of output nodes with the highest number of switching nodes become a cut-point. Division of the node is the number of OR-terms of the number of OR-terms LE is greater than adding the input and output of the inverter converts the AND. Reduce the level, power consumption and area. The proposed algorithm to MCNC logic circuits by applying a synthetic benchmark experimental results of 13% compared to the number of logical blocks decreased. 8% of the power consumption results in a reduced efficiency of the algorithm represented been demonstrated.

• Journal of Digital Contents Society
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• v.14 no.1
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• pp.1-5
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• 2013

In this paper a study of efficient CPLD low power algorithm is proposed. Proposed algorithm applicate graph partition method using DAG. Circuit representation DAG. Each nodes set up cost. The feasible cluster create according to components of CPLD. Created feasible cluster generate power consumption consider the number of OR-term, the number of input and the number of output. Implement a circuit as select FC having the minimum power consumption. Compared with experiment [9], and power consumption was decreased. The proposed algorithm is efficient. this paper, we proposed FPGA algorithm for consider the power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.134-139
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• 2006

In this paper we present the Low-Power Bus Driven Floorplan(BDF) in which the bus power consumption is minimized by using a new cost function. The previously reported BDF has used the cost function which minimizes only the chid and the bus area. However, such a cost function may not consider the bus power consumption determined by the topology of a bus in case of the segmented bus design. In this paper, we formulate a new cost function which. reflects the communication frequency and the real distance between blocks in a bus to model the bus power consumption. For the Low-Power BDF with the new cost function, the experimental results show the bus power consumption cost is reduced by 11.43% on the average.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• ETRI Journal
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• v.34 no.5
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• pp.727-733
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• 2012

This paper demonstrates a new driving scheme that allows reducing the supply voltage of data drivers for low-power active matrix organic light-emitting diode (AMOLED) displays. The proposed technique drives down the data voltage range by 50%, which subsequently diminishes in the peak power consumption of data drivers at the full white pattern by 75%. Because the gate voltage of a driving thin film transistor covers the same range as a conventional driving scheme by means of a level-shifting scheme, the low-data supply scheme achieves the equivalent dynamic range of OLED currents. The average power consumption of data drivers is reduced by 60% over 24 test images, and power consumption is kept below 25%.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.545-546
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• 2008

This paper presents a low power CMOS low noise amplifier for UWB applications. To reduce the power consumption, two cascode amplifiers was stacked in DC. Designed with $0.18-{\mu}m$ CMOS technology, the proposed LNA achieves 20dB flat gain, below 3dB noise figure, and the power consumption of 5.2mW from a 1.8 V supply voltage.