• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.3 s.303
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• pp.53-62
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• 2005

In the decoding process of interframe Wavelet coding, the Wavelet transform requires huge computational complexity. Since the decoder may need to be used in various devices such as PDAs, notebooks, or PC, the decoder's complexity should be adapted to the processor's computational power. So, it is natural that the low complexity codec is also required for scalable video coding. In this paper, we develop a method of controlling and lowering the complexity of the spatial Wavelet transform while sustaining the same coding efficiency as the conventional spatial Wavelet transform. In addition, the proposed method may alleviate the ringing effect for slowly changing image sequences.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.167-173
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• 2015

This paper presents a study on the Full-HD HEVC(High Efficiency Video Coding) encoder IP(Intellectual Property) design. The designed IP is for HEVC main profile 4.1, and performs encoding with a speed of 60 fps of full high definition. Before hardware and software design, overall reference model was developed with C language, and we proposed a parallel processing architecture for low-power consumption. And also we coded firmware and driver programs relating IP. The platform for verification of developed IP was developed, and we verified function and performance for various pictures under several encoding conditions by implementing designed IP to FPGA board. Compared to HM-13.0, about 35% decrease in bit-rate under same PSNR was achieved, and about 25% decrease in power consumption under low-power mode was performed.

• Journal of Broadcast Engineering
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• v.18 no.6
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• pp.808-815
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• 2013

In this paper, we propose a novel fast and low-complexity Motion Estimation (ME) algorithm for Ultra High Definition (UHD) High Efficiency Video Coding (HEVC). Motion estimation occupies 77~81% of the amount of computation in HEVC. After all, the main key of video codec implementation is to find a fast and low-complexity motion estimation algorithm and architecture. We analyze the previous motion estimation algorithms and propose three optimal algorithm to reduce the computation proportion for HEVC. The proposed algorithm uses only 0.36% of the amount of operations compared to full search algorithm while maintaining compression performance with slight loss of 1.1%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.891-901
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• 2003

This paper presents low-power asynchronous barrel shifters for variable length encoders and decoders useful in portable applications using multimedia standards. Our approach is to create multi-level asynchronous barrel shifters optimized for the skewed shift control statistics often found in these codecs. For common shifts, data passes through one level, whereas for rare shifts, data passes though multiple levels. We compare our optimized designs with the straightforward asynchronous and synchronous designs. Both pre- and Post-layout HSPICE simulation results indicate that, compared to their synchronous counterparts, our designs provide over a 40% savings in average energy consumption for a given average performance.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.727-729
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• 2002

In this paper, we proposed quad variable rates ADPCM coding method and its implementation on C6000 DSP, which is modified from the standard ADPCM of ITU G.726 for speech quality improvement considering the environmental noise Four coding rates, 16Kbps, 24Kbps, 32Kbps and 40Kbps are used for speech window samples and the rate decision threshold is decided by the environmental noise level. The object of the proposed method is to reduce the coding rate while retaining the speech quality and the speech quality is considerably close to 40Kbps single rate coder with the coding rate close to 16Kbps single rate coder under the environmental noise. The environmental noise level affects the coding rate and the noise level is calculated per every speech window samples. At high noise level, more samples are coded at higher rates to enhance the quality, but at low noise level, only the big speech signals are coded at higher rates and more speech samples are coded at lower coding rates to reduce the coding rates. The influence of the noise on tile speech signal is considerably high for small signals and the small signal has the higher ZCR (zero crossing rate). The method is simulated in PC and to be implemented on C6000 floating point DSP board in real time operations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.455-463
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• 2001

In this Paper, an approximate processing method is proposed and tested. The proposed method uses variable CSD (VCSD) coefficients which approximate filter stopband attenuation by controlling the precision of the CSD coefficient sets. A decimation filter for Audio Codec '97 specifications has been designed having processor architecture that consists of program/data memory, arithmetic unit, energy/level decision, and sinc filter blocks, and fabricated with 0.6${\mu}{\textrm}{m}$ CMOS sea-of-gate technology. For the combined two halfband FIR filters in decimation filter, the number of addition operations were reduced to 63.5%, 35.7%, and 13.9%, compared to worst-case which is not an adaptive one. Experimental results show that the total power reduction rate of the filter is varying from 3.8 % to 9.0 % with respect to worst-case. The proposed approximate processing method using variable CSD coefficients is readily applicable to various kinds of filters and suitable, especially, for the speech and audio applications, like oversampling ADCs and DACs, filter banks, voice/audio codecs, etc.