The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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Statistically Optimized Asynchronous Barrel Shifters for Variable Length Codecs

통계적으로 최적화된 비동기식 가변길이코덱용 배럴 쉬프트

  • Peter A. Beerel (University of Southern California, EE-systems Dept., Asynchronous CAD Group) ;
  • Kim, Kyeoun-Soo
  • Published : 2003.11.01
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Abstract

This paper presents low-power asynchronous barrel shifters for variable length encoders and decoders useful in portable applications using multimedia standards. Our approach is to create multi-level asynchronous barrel shifters optimized for the skewed shift control statistics often found in these codecs. For common shifts, data passes through one level, whereas for rare shifts, data passes though multiple levels. We compare our optimized designs with the straightforward asynchronous and synchronous designs. Both pre- and Post-layout HSPICE simulation results indicate that, compared to their synchronous counterparts, our designs provide over a 40% savings in average energy consumption for a given average performance.

본 논문은 다양한 멀티미디어 표준들을 이용하는 휴대용 기기에 유용한 가변길이 인코더와 디코더의 저 전력 비동기식 배럴 쉬프터를 제시한다. 본 논문의 새로운 접근 방법은, 보통 가변길이 코덱의 불균일한 쉬프트 제어에 대해서 통계적으로 최적화 된 다중레벨의 비동기식 배럴 쉬프터를 도출하는 것이다. 자주 발생하는 쉬프트에 대해서는 데이터가 하나의 레벨만 통과하면 출력되도록 하고, 드물게 나타나는 쉬프트에 대해서는 데이터가 다중레벨의 통과하여 출력되도록 구성한다. 레이아웃 전과 후의 HSPICE 시뮬레이션 결과에 대해서, 제안된 설계는 최적화 과정을 거치지 않은 비동기식 설계 및 동기식 설계와 비교해서, 동일한 성능(평균적인) 하에서 40%이상의 에너지 소모(평균적인)를 절약할 수 있었다.

Keywords

References

  1. K. P. Acken, M J. Irwin, and R. M. Owens, 'Power comparisons for barrel shifters,' International Symposium on Low Power Electronics and Design, pp. 209-212, 1996
  2. M Benes, S. M. Nowick, and A Wolfe, 'A fast asynchronous Huffman decoder for compressed-code embedded processors,' Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1998
  3. M. Benes, A Wolfe, and S. M Nowick, 'A high-speed asynchronous decompression circuit for embedded processors,' Advanced Research in VLSI, pp. 219-236, Sept. 1997
  4. E. Brunvand, S. Nowick, and K. Yun, 'Practical advances in asynchronous design,' Proc. International Conf. Computer Design (ICCD), pp. 662-668, 1997
  5. S. Cho, T. Xanthopoulos, and A. Chandrakasan, 'An ultra low power variable length decoder for MPEG-2 exploiting codeword distribution,' IEEE Custom Integrated Circuits Conference, pp. 177-180, 1998
  6. W Chou, P. A Beerel, R Ginosar, R.Kol, C. J. Myers, S. Rotem, K. Stevens, and K. Y. Yun, 'Average-case optimized technology mapping of one-hot domino circuits,' Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1998
  7. M Horowitz, 'EE271, introduction to VLSI systems, lecture notes,' http://www.stanford.edu/class/ee271, 1999.
  8. S. M Kang, 'Domino-CMOS barrel switch for 32-bit VLSI processors,' IEEE Circuits and Devices Magazine, pp. 3-8, May 1987
  9. S.-M Lei and M-T. Sun, 'An entropy coding system for digital HDTV applications,' IEEE Transactions on Video Technology, pp.147-155, March 1991
  10. C. H. lin and C. W. Jen, 'Low power parallel Huffman decoding,' lEE Electronic Letters, pp. 240-241, Feb. 1998
  11. The MOSIS service. http://www.mosis.org, 1999
  12. S. M. Nowick, 'Design of a low-latency asynchronous adder using speculative completion,' lEE Proceedings of Computers and Digital Techniques, vol. 143, no. 5, pp. 301-307, Sept. 1996 https://doi.org/10.1049/ip-cdt:19960704
  13. S. M. Nowick, K. Y. Yun, and P. A. Beerel, 'Speculative completion for the design of high-performance asynchronous dynamic adders,' Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, Apr. 1997
  14. R Pereira, 'Fully pipelined TSPC barrel shifter for high-speed applications,' IEEE Journal of Solid-State Circuits, pp. 686-690, June 1995
  15. R. Pillai, D. Al-Khalili, and A. Al-Khalili, 'Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition,' International Symposium on Low Power Electronics and Design, pp. 235-238, 1997
  16. S. Rotem, K. Stevens, R. Ginosar, P. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, M. Roncken, and B. Agapiev, 'Rappid: An asynchronous instruction length decoder,' Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, Apr. 1999
  17. C. L. Seitz, 'System timing,' C. A. Mead and L. A. Omway, Introduction to VLSI Systems, chapter 7, Addison-Wesley, 1980
  18. G. M Tharakan and S. M Kang, 'A new design of a fast barrel switch network,' IEEE Journal of Solid-State Circuits, pp. 217-221, Feb. 1992
  19. G. M Tharakan and S. M Kang, 'A new design of a fast barrel switch network,' IEEE Journal of Solid-State Circuits, pp. 217-221, Feb. 1992
  20. N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 2nd edition, 1993
  21. T. Williams, ISSCC96 tutorial: Dynamic logic: Clocked and asynchronous, 1996
  22. S. J. Yih, M Cheng, and W-S. Feng, 'Multilevel barrel shifter for CORDIC design,' lEE Electronic Letters, pp. 1178-1179, June 1996
  23. K. Y. Yun, A. E. Dooply, J. Arceo, P. A. Beerel, and V. Vakilotojar, 'The design and verification of a high-performance low-control-overhead asynchronous differential equation solver,' Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, April 1997