• Proceedings of the KIPE Conference
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• 1996.06a
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• pp.117-120
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• 1996

Power conversion system must be increased switching frequency in order to achieve a small size, a light weight and a low noise. However, the switches of converter are subjected to high switching power losses and switching stresses. As a result of those, the power system brings on a low efficiency. In this paper, the authors propose a DC-DC boost converter of high power by partial resonant switch method (PRSM). The switching devices in a proposed circuit are operated with soft switching and the control technique of those is simplified for switch to drive in constant duty cycle. The partial resonant circuit makes use of a inductor using step up and a condenser of loss-less snubber. Also the circuit has a merit which is taken to increase of efficiency, as it makes to a regeneration at input source of accumulated energy in snubber condenser without loss of snubber in conventional circuit. The result is that the switching loss is very low and the efficiency of system is high. The proposed converter is deemed the most suitable for high power applications where the power switching devices are used.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.410-415
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• 2014

This paper presents a new rectifier with a bootstrapping technique to reduce the effective drop voltage. An all-digital delay locked loop (ADDLL) circuit was also applied to prevent the reverse leakage current. The proposed rectifier uses NMOS diode connected instead of PMOS to reduce the design size and improve the frequency respond. All the sub-circuits of ADDLL were designed with low power consumption to reduce the total power of the rectifier. The rectifier was implemented in CMOS $0.35{\mu}m$ technology. The peak power conversion efficiency was 76 % at an input frequency of 6.78MHz and a power level of 5W.

• Journal of Power Electronics
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• v.9 no.2
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• pp.173-179
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• 2009

This paper proposes a new three-phase diode rectifier system with a sinusoidal input current at unity power factor and a regulated and isolated output voltage at low level. The inherent natural wave-shaping capability of the reduced kVA polyphase transformer together with an active current wave-shaping technique results in a significant reduction of input and output filter requirements associated with switching ripple and EMI. The operation principles are described along with a design example and a comparative evaluation. Experimental results on a 1.5kW prototype are provided to validate the proposed concept.

• Journal of Advanced Marine Engineering and Technology
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• v.25 no.4
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• pp.833-845
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• 2001

Quantitative Feedback Theory(QFT) has been used to design a robust power system stabilizer(PSS) to improve transient and dynamic stabilities of a power system. This design technique is basically accomplished in frequency domain. The most important feature of QFT is that it is able to deal with the design problem of complicated uncertain plants. A basic idea in QFT design is the translation of closed-loop frequency-domain specifications into Nichols chart domains specifying the allowable range of the nominal open-loop response and then to design a controller by using the gain-phase loop shaping technique. This paper introduces a new algorithm to compute QFT bounds more efficiently. The propose QFT design method ensures a satisfactory performance of the PSS under a wide range of power system operating conditions.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.492-498
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• 2017

In this paper, we integrate a divide-by-3 injection-locked frequency divider (ILFD) in CMOS technology with a $0.18-{\mu}m$ BiCMOS process. We propose a self-injection technique that utilizes harmonic conversion to improve the locking range, phase-noise, and input sensitivity simultaneously. The proposed self-injection technique consists of an odd-to-even harmonic converter and a feedback amplifier. This technique offers the advantage of increasing the injection efficiency at even harmonics and thus realizes the low-power implementation of an odd-order division ILFD. The measurement results using the proposed self-injection technique show that the locking range is increased by 47.8% and the phase noise is reduced by 14.7 dBc/Hz at 1-MHz offset frequency with the injection power of -12 dBm. The designed divide-by-3 ILFD occupies $0.048mm^2$ with a power consumption of 18.2-mW from a 1.8-V power supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.451-454
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• 2015

This paper introduces 3 type of OTAs with $0.35-{\mu}m$ standard CMOS technology for Low-Power, Low-Voltage. The first type is a two-stage OTA designed to operate with a 1-V VDD and it has $1.774{\mu}W$ low power consumption. All transistors are operating in strong inversion. It takes Gm-Enhancement techniques to compensate gm, which is lowered by Bulk-Driven technique and has an Wide swing current mirror for low voltage operation and a Class-A output. The second type is a Two-stage OTA designed to operate with a 0.8-V VDD and It has 52nW low power consumption and 112dB high gain. The current mirror uses Composite Transistor binding Gates of two MOSFET to raise Rout which is similar with cascode structure. The third type is a Two-stage OTA designed to operate with a 0.6-V VDD and It has 160nW low power consumption and 72dB high gain. It takes Level Shift technique by Common Gate structure to amplify signals without additional bias voltage at second stage.

• Journal of IKEEE
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• v.16 no.4
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• pp.283-289
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• 2012

In this paper, We proposed Separate Gate Technique(SGT) to improve the switching characteristics of Trench power MOSFET. Low gate-to-drain 전하 (Miller 전하 : Qgd) has to be achieved to improve the switching characteristics of Trench power MOSFET. A thin poly-silicon deposition is processed to form side wall which is used as gate and thus, it has thinner gate compared to the gate of conventional Trench MOSFET. The reduction of the overlapped area between the gate and the drain decreases the overlapped charge, and the performance of the proposed device is compared to the conventional Trench MOSFET using Silvaco T-CAD. Ciss(input capacitance : Cgs+Cgd), Coss(output capacitance : Cgd+Cds) and Crss(reverse recovery capacitance : Cgd) are reduced to 14.3%, 23% and 30% respectively. To confirm the reduction effect of capacitance, the characteristics of inverter circuit is comprised. Consequently, the reverse recovery time is reduced by 28%. The proposed device can be fabricated with convetional processes without any electrical property degradation compare to conventional device.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.62-66
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• 2016

This paper presents a MedRadio-band low power low noise amplifier for Medical Devices. A proposed MedRadio-band low power low noise amplifier adopts a current-reuse resistive feedback topology to increase overall gm and reduce power consumption. The gain of the LNA increases by the Q-factor of the additional series RLC input matching network, and its noise figure is minimized by the similar factor. Furthermore, it consumes low power because of low supply voltage and current reuse technique. By exploiting the $g_m$-booting and matching network property, the proposed MedRadio-band low noise amplifier achieves a noise figure of 0.85 dB, a voltage gain of 30 dB, and IIP3 of -7.9 dBm while consuming 0.18 mA from a 1 V supply voltage in $0.13{\mu}m$ CMOS technology.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.12
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• pp.1798-1802
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• 2013

We present a technique for measuring low resistance ranges of a decade resistor with a 4-Terminal connection. With the technique the accuracy of 0.8 % was obtained for a 1 $m{\Omega}$ resistance of the decade resistor. We suggested a proper pattern 4-Terminal measurement results with several 4-Terminal pattern and adapters. Additionally, we should that precise measurements for low resistance can be made usung a digital multimeter(DMM) only.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.399-402
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• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.