• Journal of Electrical Engineering and Technology
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• v.2 no.1
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• pp.29-34
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• 2007

The input and output impedances in a low voltage distribution system is one of the most important matters for power line communication because from the viewpoint of communication, the attenuation characteristic of the high frequency signals is greatly caused by impedance mismatch during sending and receiving. The frequency range is from 1MHz to 30MHz. Therefore, this paper investigates the input and output impedances in order to understand the characteristic of high frequency signals in the low voltage distribution system between a pole transformer and an end user. For power line communication, the model of Korea's low voltage distribution system is proposed in a residential area and then the low voltage distribution system is set up in a laboratory. In the low voltage distribution system, S parameters are measured by using a network analyzer. Finally, input and output impedances are calculated using S parameters.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1826-1829
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• 2005

Recent advancement in wireless communications and electronics has enabled the development of low power sensor network. Wireless sensor network are often used in remote monitoring control applications, health care, security and environmental monitoring. Wireless sensor networks are an emerging technology consisting of small, low-power, and low-cost devices that integrate limited computation, sensing, and radio communication capabilities. Sensor network platform for health care has been designed, fabricated and tested. This system consists of an embedded micro-controller, Radio Frequency (RF) transceiver, power management, I/O expansion, and serial communication (RS-232). The hardware platform uses Atmel ATmega128L 8-bit ultra low power RISC processor with 128KB flash memory as the program memory and 4KB SRAM as the data memory. The radio transceiver (Chipcon CC1000) operates in the ISM band at 433MHz or 916MHz with a maximum data rate of 76.8kbps. Also, the indoor radio range is approximately 20-30m. When many sensors have to communicate with the controller, standard communication interfaces such as Serial Peripheral Interface (SPI) or Integrated Circuit ($I^{2}C$) allow sharing a single communication bus. With its low power, the smallest and low cost design, the wireless sensor network system and wireless sensing electronics to collect health-related information of human vitality and main physiological parameters (ECG, Temperature, Perspiration, Blood Pressure and some more vitality parameters, etc.)

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.426-432
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• 2012

A fully-integrated low power K-band radar transceiver in 130 nm CMOS process is presented. It consists of a low-noise amplifier (LNA), a down-conversion mixer, a power amplifier (PA), and a frequency synthesizer with injection locked buffer for driving mixer and PA. The receiver front-end provides a conversion gain of 19 dB. The LNA achieves a power gain of 15 dB and noise figure of 5.4 dB, and the PA has an output power of 9 dBm. The phase noise of VCO is -90 dBc/Hz at 1-MHz offset. The total dc power dissipation of the transceiver is 142 mW and the size of the chip is only $1.2{\times}1.4mm^2$.

• Journal of Korea Multimedia Society
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• v.24 no.9
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• pp.1211-1223
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• 2021

Internet of Things(IoT) services have increased the demand for connectivity among electronics devices. As a result, various types of novel wireless communication technologies have been standardized and developed. In this paper, we evaluate the performance of low power wireless communication technologies such as Bluetooth, IEEE 802.15.4, DASH 7, IEEE 802.15.4g, LoRa, and SigFox in various environments. This is the first experiment evaluating various low power wireless communication technologies in real testbed. We expect that the evaluation results will be useful data to other researchers in applying the IoT technology in the future.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.75-79
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• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.103-106
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• 2000

In this paper a communication system that is not using the communication line but power line is presented. It will be very useful for an information-oriented society with tele-metering and home automation. Conventional system has a difficulty in transmitting information due to decreasing communication voltage and increasing carrier, current. Proposed idea is a special type switching amplifier system which has a low inner resistance. It can provide reactive power and dose not have low impedance between the transceivers. This new system is proposed to overcome the loss of conductor load in a PLC system.

• ETRI Journal
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• v.38 no.5
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• pp.885-895
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• 2016

The lowest power mode (passive-standby mode) was proposed for reducing the power consumption of set-top boxes in a standby state when not receiving content. However, low-power set-top boxes equipped with the lowest power mode have been rarely commercialized because of their low-quality user experience. In the lowest power mode, they deactivates almost all of operational modules and processes, and thus require dozens of seconds for activation latency (that is, the latency for activating all modules of the set-top boxes in a standby state). They are not even updated in a standby state because they deactivate their network interfaces in a standby state. This paper proposes an adaptive standby mode scheduling method for improving the user experience of such boxes. Set-top boxes using the proposed method can analyze the activation pattern and find the frequently used time period (that is, when the set-top boxes are frequently activated). They prepare for their activation during this frequently used time period, thereby reducing the activation latency and enabling their update in a standby state.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.11
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• pp.5381-5399
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• 2016

Currently, the quantize-and-forward (QF) scheme with high order modulation and quantization has rather high complexity and it is thus impractical, especially in multiple relay cooperative communications. To overcome these deficiencies, an improved low complex QF scheme is proposed by the combination of the low order binary phase shift keying (BPSK) modulation and the 1-bit and 2-bit quantization, respectively. In this scheme, the relay selection is optimized by the best relay position for best bit-error-rate (BER) performance, where the relays are located closely to the destination node. In addition, an optimal power allocation is also suggested on a total power constraint. Finally, the BER and the achievable rate of the low order 1-bit, 2-bit and 3-bit QF schemes are simulated and analyzed. Simulation results indicate that the 3-bit QF scheme has about 1.8~5 dB, 4.5~7.5 dB and 1~2.5 dB performance gains than those of the decode-and-forward (DF), the 1-bit and 2-bit QF schemes, at BER of $10^{-2}$, respectively. For the 2-bit QF, the scheme of the normalized Source-Relay (S-R) distance with 0.9 has about 5dB, 7.5dB, 9dB and 15dB gains than those of the distance with 0.7, 0.5, 0.3 and 0.1, respectively, at BER of $10^{-3}$. In addition, the proposed optimal power allocation saves about 2.5dB much more relay power on an average than that of the fixed power allocation. Therefore, the proposed QF scheme can obtain excellent features, such as good BER performance, low complexity and high power efficiency, which make it much pragmatic in the future cooperative communications.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.416-424
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• 2014

This paper presents an 8-bit pipelined analog-to-digital converter. The supply voltage applied for comparators and other sub-blocks of the ADC were 0.7V and 0.5V, respectively. This low power ADC utilizes the capacitive charge pump technique combined with a source-follower and calibration to resolve the need for the opamp. The differential charge pump technique does not require any common mode feedback circuit. The entire structure of the ADC is based on fully dynamic circuits that enable the design of a very low power ADC. The ADC was designed to operate at 1MS/s in 90nm CMOS process, where simulated results using ADS2011 show the peak SNDR and SFDR of the ADC to be 47.8 dB (7.64 ENOB) and 59 dB respectively. The ADC consumes less than 1mW for all active dynamic and digital circuitries.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.89-95
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• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.