• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.545-546
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• 2008

This paper presents a low power CMOS low noise amplifier for UWB applications. To reduce the power consumption, two cascode amplifiers was stacked in DC. Designed with $0.18-{\mu}m$ CMOS technology, the proposed LNA achieves 20dB flat gain, below 3dB noise figure, and the power consumption of 5.2mW from a 1.8 V supply voltage.

• Journal of Korea Society of Industrial Information Systems
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• v.6 no.4
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• pp.48-53
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• 2001

A three-stage low noise amplifier(LNA) for the Base-station of the IMT-2000 is designed and implemented. In the first stage, a GaAs HJt-FET which has good noise characteristics is made use of. Monolithic microwave integrated circuits(MMICS) are used in the second and the third stage to achieve both the high gain and high output power. Although the balanced amplifier is used to reduce the input VSWR, it is done only in the first stage because we have to minimize the noise figure attributed to the phase difference of the balanced amplifier. It is shown that the implemented LNA has the gai over 39.74dB, the gain flatness less than ±0.4dB, the noise figure below 0.97dB, input and output VSWRs less than 1.2, and OIP₃(output third order intercept point) of 38.17dBm in the operating frequency range.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1601-1602
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• 2006

A cascode low noise amplifier(LNA) for a 2.45GHz RFID reader is designed using 0.25um CMOS technology. There are four LNA design techniques applied to the cascode topology. In this paper, power-constrained simultaneous noise and input matching(PCSNIM) technique is used for low power consumption and achieving the noise matching and input matching simultaneously. Simulation results demonstrate a noise figure of 2.75dB, a power gain of 10.17dB, and a dissipation power of 8.65mW with 1V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.45-51
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• 2011

This paper presents a wideband low-noise amplifier (LNA) covering 800MHz~5.8GHz for various wireless communication standards by utilizing in a 0.13um CMOS technology. Particularly, the LNA consists of two stages to improve the low-noise characteristics, that is, a cascode input stage and an output buffer with noise cancellation technique. Also, a feedback resistor is exploited to help achieve wideband impedance matching and wide bandwidth. Measure results demonstrate the bandwidth of 811MHz~5.8GHz, the maximum gain of 11.7dB within the bandwidth, the noise figure of 2.58~5.11dB. The chip occupies the area of $0.7{\times}0.9mm^2$, including pads. DC measurements reveal the power consumption of 12mW from a single 1.2V supply.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.35-38
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• 2008

In this paper, study noise performance of LNA to enhance Q-factor of input circuit by patterned ground shield is inserted inductor using TSMC 0.18um. Applied LNA technology is cascode method. The input matching circuit was constituted on-chip and wirebonding inductor. Taguchi's method is used for the best suited structure of PGS. We confirmed enhancement of Q-factor by inserted PGS into inductor. The input matching circuit enhanced Q-factor by inductor with PGS improve noise figure of LNA.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.9 no.4
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• pp.141-146
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• 2010

In this paper, bandgap reference PTAT(Proportional to Absolute Temperature) circuit and flexible gain control of LNA(Low Noise Amplifier) which is usable in Zigbee system of 2.4GHz band are designed by TSMC $0.18{\mu}m$ CMOS library. PTAT bandgap reference circuit is proposed to minimize the instability of CMOS circuit which may be unstable in temperature changes. This circuit is designed such that output voltage remains within 1.3V even when the temperature varies from $-40^{\circ}C$ to $-50^{\circ}C$ when applied to the gate bias voltage of LNA. In addition, the LNA is designed to be operated on 2.4GHz which is applicable to Zigbee system and able to select gains by changing output impedance using 4 NMOS operated switches. The simulation result shows that achieved gain is 14.3~17.6dB and NF (Noise Figure) 1.008~1.032dB.

• Journal of electromagnetic engineering and science
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• v.2 no.1
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• pp.22-27
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• 2002

This paper describes a SiGe HBT low noise amplifier (LNA) design for IMT-2000 mobile applications. This LNA is optimized for linearity in consideration of the out-of-band-termination capacitance. This LNA yields a noise figure of 1.2 dB, 16 dB gain, an input return loss of 11 dB, and an output return loss of 14.3 dB over the desired frequency range (2.11-2.17 GHz). When the RF input power is -2i dBm, the input third order intercept point (IIP3) of 8.415 dBm and the output third order intercept point (OIP3) of 24.415 dBm are achieved.

• Journal of Korea Multimedia Society
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• v.6 no.1
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• pp.161-166
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• 2003

This paper presents a high gain LNA for a bluetooth application using 0.25$\mu\textrm{m}$ CMOS technology. The conventional one stage LNA has a low power gain. The presented one stage LNA using a cascode inverter LNA with a voltage reference and without a choke inductor has an improved Power gain. Simulation results of the 2.4GHz designed LNA shows a high power gain of 21dB, a noise figure of 2.2dB, and the power consumption of 255mW at 2.5V power supply.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.833-836
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• 1999

In this paper, a wideband MMIC LNA was designed using low Q matching network. Gains of 9.8~12.2 ㏈, and noise figures of 1.7~2.1 ㏈ were obtained from the fabricated wideband MMIC LNA in the frequency ranges of 1.5~2.5㎓. And maximum output power of 10.83 ㏈m were obtained at the center frequency of 2 ㎓. The chip size of the fabricated wideband MMIC low noise amplifier is 1.4 mm$\times$1.4 mm.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.385-388
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• 2000

본 논문에서는 좀더 효율적이고 소형화한 GPS(Global Positioning System)용 안테나와 LNA(Low Noise Amplifier)를 IMT-2000 단말기에 내장함으로써 개인 휴대 통신 기능과 더불어 좀 더 정확한 위치추적 기능을 동시에 가능케 하고자 한다. 중심 주파수 1.575 GHz의 저잡음 증폭기와 안테나의 크기는, 합쳐서 10$\times$10$\times$4 (mm)로서 상층은 마이크로스트립 패치 안테나이고, 중간층은 안테나 ground와 LNA ground의 공통 ground이며, 제일 아래층에는 LNA가 위치하게 된다. LNA 의 경우 2단을 중첩하여, 첫째 단 16dB, 둘째 단 18dB의 이득 특성을 보였는데 첫째, 둘째 단의 대역통과 필터에서 삽입손실로 3dB의 손실을 가져와 총 3dB의 이득 특성을 보였다. 잡음 특성은 약 1.9의 특성을 보였다. 안테나의 경우 9$\times$9$\times$$\times$2 (mm)로써, 고유전율( $\varepsilon$$_{r}$ = 73 )의 세라믹을 사용하여 그 크기를 상당부분 줄였다. 그리고 유전체 밑의 ground를 옆면까지 높임으로써 좀 더 소형화한 안테나를 가능케 하였다. 고유전율의 유전체를 사용하였기에 안테나 자체의 이득 특성은 저잡음 증폭기에서 보상하고, 안테나의 임피던스 정합 또한 LNA의 입력 쪽에서 하도록 하였다. 또한 위성신호 수신을 위해 안테나는 RHCP 의 원형편파 특성을 갖는다.