• 한국전자파학회논문지
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• 제29권5호
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• pp.393-396
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• 2018

본 논문은 65-nm 저전력 CMOS 공정을 이용해 94 GHz 대역 저잡음 증폭기를 설계한 결과를 제시한다. 설계한 저잡음 증폭기는 4단 차동 공통소스 구조를 가지며, 트랜스포머를 사용해 각 단 및 입출력 임피던스 정합 회로를 구성했다. 제작한 저잡음 증폭기는 94 GHz에서 최대 전력 이득 25 dB을 보이며, 3-dB 대역폭은 5.5 GHz이다. 제작한 칩의 면적은 패드를 포함해 $0.3mm^2$이며, 1.2 V 공급 전원에서 46 mW의 전력을 소비한다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2006년도 춘계종합학술대회
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• pp.259-262
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• 2006

본 논문에서는 2.4 GHz ZigBee 응용을 위한 저전력 CMOS LNA(Low Noise Amplifier)를 설계하였다. 제안된 회로의 설계에서 TSMC $0.18{\mu}m$ CMOS 공정을 사용하였고 current-reused stage를 이용한 2단 cascade 구조를 채택하였다. 본 논문에서는 LNA 설계 과정을 소개하고 ADS(Advanced Design System)를 이용한 모의실험 결과를 제시하여 검증하였다. 모의실험 결과, 1.0V의 전압이 인가될 때 1.38mW의 매우 낮은 전력 소모를 확인하였다. 또한 13.83dB의 최대 이득, -20.37dB의 입력 반사 손실, -22.48dB의 출력 반사 손실 그리고 1.13dB의 잡음 지수를 보였다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2003년도 춘계종합학술대회
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• pp.386-389
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• 2003

본 논문에서는 Bluetooth applications를 위한 Bipolar Transistor low noise amplifier (LNA)를 설계하였다. 설계된 LNA는 2.4GHz에서 14.31[dB]의 Gain과 1.59[dB]의 NF를 보였다. 또한 S11은 -13.5[dB], S22는 -21.4[dB]의 양호한 값은 보였다.

• 한국전자파학회논문지
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• 제24권11호
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• pp.1098-1103
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• 2013

본 논문은 직렬 RLC 정합과 저항 궤환 회로를 이용하여 설계한 중심 주파수 8 GHz를 갖는 저잡음 증폭기를 제안한다. 제안하는 LNA는 입력 정합에 Degenerate inductor를 사용하여 $S_{21}$이 넓은 대역폭을 지니고 있고, 병렬로 구성된 회로를 직렬 공진 회로로 변환함으로써 입력 정합 회로를 등가회로로 축약하여 해석을 하였다. 저항 궤환 회로와 입력 RLC 정합이 모두 사용되어 제안하는 LNA는 최대 8.5 dB의 $S_{21}$(-3 dB 대역폭은 약 3.5 GHz), 잡음 지수로 5.9 dB, IIP3로는 1.6 dBm 값을 가지며, 1.2 V에서 7 mA를 소모한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1599-1600
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• 2006

In this paper, a small size, $7{\times}6\;mm^2$, Low Noise Amplifier(LNA) using LTCC process was fabricated with multi-layer structure for 2.4GHz wireless LAN. The measured results demonstrate that the bandwidth is 130 MHz, and the operating frequency is from 2.39GHz to 2.52GHz. The power gain is above 7.3 dB in the operating frequency range and the gain flatness is 0.5 dB. The maximum S11 is -4 dB and the maximum S22 is -7.5 dB. The noise figure is less than 1.83 dB. The measured power gain, S11 and S22 were had poorer performance than the simulation results. The reason for this discrepancy is that the input and output matching was not performed exactly. However, the noise figure of the LTCC low noise amplifier is better than simulation result. It is found that it is possible to fabricate a LTCC low noise amplifier in a small size.

• ETRI Journal
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• 제36권3호
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• pp.510-513
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• 2014

A Q-band pHEMT image-rejection low-noise amplifier (IR-LNA) is presented using inter-stage tunable resonators. The inter-stage L-C resonators can maximize an image rejection by functioning as inter-stage matching circuits at an operating frequency ($F_{OP}$) and short circuits at an image frequency ($F_{IM}$). In addition, it also brings more wideband image rejection than conventional notch filters. Moreover, tunable varactors in L-C resonators not only compensate for the mismatch of an image frequency induced by the process variation or model error but can also change the image frequency according to a required RF frequency. The implemented pHEMT IR-LNA shows 54.3 dB maximum image rejection ratio (IRR). By changing the varactor bias, the image frequency shifts from 27 GHz to 37 GHz with over 40 dB IRR, a 19.1 dB to 17.6 dB peak gain, and 3.2 dB to 4.3 dB noise figure. To the best of the authors' knowledge, it shows the highest IRR and $F_{IM}/F_{OP}$ of the reported millimeter/quasi-millimeter wave IR-LNAs.

• ETRI Journal
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• 제29권3호
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• pp.371-380
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• 2007

This paper proposes a new automatic compensation network (ACN) for a system-on-chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on-chip ACN using 0.18 ${\mu}m$ SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design-for-testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.301-306
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• 2015

An ultra-compact and wideband low noise amplifier (LNA) in a quad flat non-leaded (QFN) package is presented. The LNA monolithic microwave integrated circuit (MMIC) is implemented in a $0.25{\mu}m$ GaN IC technology on a Silicon Carbide (SiC) substrate provided by Triquint. A source degeneration inductor and a gate inductor are used to obtain the noise and input matching simultaneously. The resistive feedback and inductor peaking techniques are employed to achieve a wideband characteristic. The LNA chip is mounted in the $3{\times}3-mm^2$ QFN package and measured. The supply voltages for the first and second stages are 14 V and 7 V, respectively, and the total current is 70 mA. The highest gain is 13.5 dB around the mid-band, and -3 dB frequencies are observed at 0.7 and 12 GHz. Input and output return losses ($S_{11}$ and $S_{22}$) of less than -10 dB measure from 1 to 12 GHz; there is an absolute bandwidth of 11 GHz and a fractional bandwidth of 169%. Across the bandwidth, the noise figures (NFs) are between 3 and 5 dB, while the output-referred third-order intercept points (OIP3s) are between 26 and 28 dBm. The overall chip size with all bonding pads is $1.1{\times}0.9mm^2$. To the best of our knowledge, this LNA shows the best figure-of-merit (FoM) compared with other published GaN LNAs with the same gate length.

• 한국전자파학회논문지
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• 제9권4호
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• pp.506-514
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• 1998

능동 안테나용 X-band(11.7~12 GHz)단일 칩 초고주파 집적회로(Monolithic Microwave Integrated Circuits, MMICs) 저잡음 증폭기(Low Noise Amplifier, LNA)를 $0.15{\mu}m\times140{\mu}m$ AlGaAs/InGaAs/GaAs 고속 전자 이동도 트랜지스터(Pseudomorphic-High Electron Mobility Transistor, P-HEMT)를 이용하여 2단으로 설계하고 제작하였다. 증폭기의 안정도 특성을 위해 이득이 다소 감소하나 입력정합이 쉽고 안정도가 좋은 소스 인턱터를 사용하여 저잡음증폭기를 설계하였다. 동작 주파수에서 약 17dB의 이득, 1.3 dB의 잡음 지수 그리고 입.출력 반사손실은 -17~-15dB를 측정 결과로서 얻었다. 이러한 측정 결과는 잡음 지수를 제외하고는 설계 결과와 거의 일치하며, 제작된 MMIC LNA의 칩 크기는 $1.43\tiems1.27mm^2$이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.818-823
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• 2014

A high-gain wideband low noise amplifier (LNA) using $0.25-{\mu}m$ Gallium-Nitride (GaN) MMIC technology is presented. The LNA shows 8 GHz to 15 GHz operation by a distributed amplifier architecture and high gain with an additional common source amplifier as a mid-stage. The measurement results show a flat gain of $25.1{\pm}0.8dB$ and input and output matching of -12 dB for all targeted frequencies. The measured minimum noise figure is 2.8 dB at 12.6 GHz and below 3.6 dB across all frequencies. It consumes 98 mA with a 10-V supply. By adjusting the gate voltage of the mid-stage common source amplifier, the overall gain is controlled stably from 13 dB to 24 dB with no significant variations of the input and output matching.