• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.372-376
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• 2001

Due to several advantages of Pulse Width Modulation(PWM) Converter, such as unity power factor operation, elimination of low-order harmonics and regeneration of motor braking energy to source, the application range of PWM Converter has been rapidly extended in industrial application. Nowadays, vector control algorithm and space vector PWM(SVPWM) method are applied to improve the performances of PWM Converter, but vector control algorithm and SVPWM require to use Microprocessor and other digital devices in hardware, causing costly and somewhat large dimension system. In every practical application of energy conversion equipments, the design and implementation should be carried out considering cost and performance. High performance and low cost is the best choice for energy conversion equipments. So, this paper presents the practical design method and implementation results of 3-phase PWM Converter with analog hysteresis current controller, and verifies the performances of unit power factor operation and energy regeneration operation via experimental results.

• Journal of IKEEE
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• v.19 no.1
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• pp.45-51
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• 2015

Recently, as WPAN (Wireless Personal Area Network) becomes the necessary feature in IoT (Internet of Things) devices, the importance of data security also hugely increases. In this paper, we present the low-complexity 128-bit AES-$CCM^*$ hardware IP for IEEE 802.15.4 standard. For low-cost and low-power implementation which is essentially required in IoT devices, we propose two optimization methods. First, the folded AES(Advanced Encryption Standard) processing core with 8-bit datapath is presented where composite field arithmetic is adopted for reduced hardware complexity. In addition, to support $CCM^*$ mode defined in IEEE 802.15.4, we propose the mode-toggling architecture which requires less hardware resources and processing time. With the proposed methods, the gate count of the proposed AES-$CCM^*$ IP can be lowered up to 57% compared to the conventional architecture.

• Journal of Advanced Marine Engineering and Technology
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• v.40 no.6
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• pp.542-547
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• 2016

In recent times, Internet of Things (IoT) has attracted wide attention, and there are increasing requests for IoT application services. Open-Source Hardware (OSH) utilizes a variety of components that are created through the sharing of hardware design so that others developers can also work on it. The concept of "open source" that attracted attention in the software industry has been applied to the hardware field by the emergence of IoT market. The emergence of OSH that has the advantage of low hardware cost and faster development encourages the idea of a diverse IoT application services. In this paper, we describe an IoT application service system that is developed using the OSH platform Arduino and Raspberry Pi to process collection, exchange, and computation of the environmental information. The overall system architecture and hardware and software components are presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.12
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• pp.2820-2827
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• 2015

HSMS communication system using low-cost micro controller units(MCUs) is an essential technique for online semiconductor equipment system developments. It is intended as an alternative to SEMI E4 (SECS-I) for applications where higher speed communication is needed and the facilitated hardware setup is convenient. In this paper, an HSMS communication system using low-cost MCUS is designed and implemented. Using a MCU with a low price but high-performance as a main board, a module which processes HSMS communication is designed, and a circuit is designed to process BCR independently with a microminiature MCU. To convert tag data which is recognized from BCR into data based on HSMS communication protocol, SECS-II message is designed. Lastly, an HSMS communication system is implemented based on these designs. A low-cost HSMS communication module developed in this study can be applied in realtime monitoring and controlling system for semiconductor processes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10C
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• pp.1460-1468
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• 2004

In this paper, we developed a low-area and low-cost SIMD MAC/MAS(Single Instruction Multiple Data Multiply and ACcumulate/Multiply And Subtract) for multimedia that is used much in real life. We compared the result of this research with a previously developed more large and high performance SIMD MAC/MAS. This paper is consist of 5 parts, which are an introduction, the contents of designing SIMD MAC/MAS hardware, a special qualities for previous works, the result of synthesis and conclusion. The design result reduced by size 32% of whole hardware than 64 bit SIMD MAC/MAS block of designed for high performance. This improved ISA (Instruction Set Architecture) to be suitable to embedded DSP(Digital Signal Processor), and shortened bit range of 64-bit data to 32-bit and implement more optimally.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.3
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• pp.1058-1070
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• 2014

There are two major ways to implement depth estimation, multiple image depth estimation and single image depth estimation, respectively. The former has a high hardware cost because it uses multiple cameras but it has a simple software algorithm. Conversely, the latter has a low hardware cost but the software algorithm is complex. One of the recent trends in this field is to make a system compact, or even portable, and to simplify the optical elements to be attached to the conventional camera. In this paper, we present an implementation of depth estimation with a single image using a graphics processing unit (GPU) in a desktop PC, and achieve real-time application via our evolutional algorithm and parallel processing technique, employing a compute shader. The methods greatly accelerate the compute-intensive implementation of depth estimation with a single view image from 0.003 frames per second (fps) (implemented in MATLAB) to 53 fps, which is almost twice the real-time standard of 30 fps. In the previous literature, to the best of our knowledge, no paper discusses the optimization of depth estimation using a single image, and the frame rate of our final result is better than that of previous studies using multiple images, whose frame rate is about 20fps.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.125-126
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• 2010

In this paper, a novel multiple output converter using quasi load is proposed. Conventional multiple output converters using multi-winding transformer has poor output voltage regulations. To solve this problem, there are many proposals like post regulation method, weighted control method, and etc. However, the post regulation method regulates output voltage tightly but its conduction loss and cost are increased. And the weighted control can achieve high efficiency and low cost but its regulation is not enough. To solve these problems, this paper proposes a novel multiple output converter using quasi load. The proposed method uses a quasi load which acts like an active dummy load for tight regulation but there is rarely increase of loss and cost. The proposed method is verified by hardware test by two output(24V and 15V) flyback type converter.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.402-413
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• 2004

This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.

• Journal of Communications and Networks
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• v.1 no.3
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• pp.201-212
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• 1999

This paper studies the rapid design and implementation of the medium access control(MAC) and related interface circuits for 802.11 wireless LANs based on the field programmed gate ar-ray(FPGA) technology. Our design is thus aimed to support both the distributed coordination function (DCF) and the point coordination function(PCF) with the aid of FPGA technology. Further-more, in an infrastructure network, some stations may serve as the access points (APs) which may function like a learning bridge. This paper will also discuss how to design for such application. The hardware of the MAC and interface may at least consist of three major parts: wireless transmission and reception processes and in-terface, host(bus) interface, and the interface to the distributed system (optional). Through the increasing popularity of FPGA de-sign, this paper presents how Complex Programmable Logic De-vices(CPLD) can be utilized for speedy design of prototypes. It also demonstrates that there is much room for low-cost hardware prototype design to accelerate the processing speed of the MAC control function and for field testing.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.123-126
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• 2004

Demands on dealing with multimedia data through the network have been increased, and networking multimedia devices require processing, transmitting , and receiving the digital data. In order to implement the network for high performance and low cost, we may have to integrate the dedicated hardware into a system on a chip by spending an extra amount of silicon resource. In this paper, we describe hardware implementation of TCP/IP protocol stack which is now popular to connect multiple PCs and peripherals by means of networks. For evaluation we used ALTERA APEX 20K600EBC652 FPGA with 600,000 gates. The operating frequency is estimated 29.9MHz and it used area of $26\%$.