• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.2
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• pp.110-118
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• 2008

The regulated peak power tracking (RPPT) systems such as the series structure and the parallel structure are commonly used in the satellite space power system. However, this structure processes the solar array power to the load through two regulators during one orbit cycle, which reduces the energy transfer efficiency. The series-parallel structure for the RPPT system can improve the power conversion efficiency, but an additional regulator increases the cost, size and weight of the system. In this paper, a simplified series-parallel space power system that consists of two regulators is proposed. The proposed system has the similar energy transfer efficiency with the series-parallel structure by adding one switch to the series structure, which reduces the cost, size and the weight. The large signal stability analyses is provided to understand the four main modes of system operation. In order to compare the energy efficiency with a series structure, the simulation is performed. The experimental verifications are performed using a prototype hardware with TMS320F2812 DSP and 200W solar arrays.

• Journal of Bio-Environment Control
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• v.6 no.4
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• pp.242-249
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• 1997

Environmental control operations have been considerably contributed to the reduction of labor cost in both plastic film and glass greenhouses since government supported projects were begun. However, some problems are still remaining on the optimal environmental control and excessive operation due to an inflexible software regulating ventilation gear - reducers. The unadjustable software caused the damage of ventilation system, resulting in heat stresses of crops. This study was performed to develop a ventilation software controlling the vent opening level, opening sequence, based on the wind direction, and control interval according to the difference between ambient and set- up temperatures. The software included a beeper system alarming urgent cases, while a manager was remote from the greenhouse. A compatible hardware with the software was also developed by using a low-cost diffused DSP controller.

• International Journal of Fluid Machinery and Systems
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• v.5 no.3
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• pp.134-142
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• 2012

The competition to deliver ultra-low emitting vehicles at a reasonable cost is driving the automotive industry to invest significant manpower and test laboratory resources in the design optimization of increasingly complex exhaust after-treatment systems. Optimization can no longer be based on traditional approaches, which are intensive in hardware use and laboratory testing. The CFD is in high demand for the analysis and design in order to reduce developing cost and time consuming in experiments. This paper describes the development of a comprehensive practical model based on experiments for simulating the performance of automotive three-way catalytic converters, which are employed to reduce engine exhaust emissions. An experiment is conducted to measure species concentrations before and after catalytic converter for different loads on engine. The model simulates the emission system behavior by using an exhaust system heat conservation and catalyst chemical kinetic sub-model. CFD simulation is used to study the performance of automotive catalytic converter. The substrate is modeled as a porous media in FLUENT and the standard k-e model is used for turbulence. The flow pattern is changed from axial to radial by changing the substrate model inside the catalytic converter and the flow distribution and the conversion efficiency of CO, HC and NOx are achieved first, and the predictions are in good agreement with the experimental measurements. It is found that the conversion from axial to radial flow makes the catalytic converter more efficient. These studies help to understand better the performance of the catalytic converter in order to optimize the converter design.

• Journal of IKEEE
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• v.17 no.3
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• pp.352-359
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• 2013

This paper proposes an entropy coding unit for H.264/AVC baseline profile. Entropy coding requires code tables for macroblock encoding. There are patterns in codewords of each code tables. In this paper, the patterns between codewords are analyzed to reduce the hardware cost. The entropy coding unit consists of Exp-Golomb unit and CAVLC unit. The Exp-Golomb unit can process five code types in a single unit. It can perform Exp-Golomb processing using only two adders. While typical CAVLC units use various code tables which require large amounts of resources, the sizes of the tables are reduced to about 40% or less of typical CAVLC units using relationships between table elements in the proposed CAVLC unit. After the Exp-Golomb unit and the CAVLC unit generate code values, the entropy unit uses a small size shifter for bit-stream generation while typical methods are barrel shifters.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.11 no.4
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• pp.279-285
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• 2017

In this study, feasibility analysis was performed by estimating the costs and effects of daisy reading auxiliary machine development project. The development cost of a Daisy player device, hardware/prototype and software, with only essential functions and with low price was estimated to be \307,101,664, and the production cost for a player was calculated to be \112,000. The development of Daisy viewer software and input/output assistive devices, application, was estimated to be \284,294,08, and an input/output device was set a price of \6,600. Based on these results, we looked at the economic ripple effects on the people with disabilities by promoting daisy - reading assistive device development project. The results of this study could be used to determine whether the project is to proceed. It is expected that it provides valuable information to actively cope with the changing business environment in the future.

• Journal of Power Electronics
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• v.17 no.4
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• pp.1037-1047
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• 2017

The Differential Power Processing (DPP) converter is a promising multi-module photovoltaic inverter architecture recently proposed for photovoltaic systems. In this paper, a DPP converter architecture, in which each PV-panel has its own DPP converter in shunt, performs distributed maximum power point tracking (DMPPT) control. It maintains a high energy conversion efficiency, even under partial shading conditions. The system architecture only deals with the power differences among the PV panels, which reduces the power capacity of the converters. Therefore, the DPP systems can easily overcome the conventional disadvantages of PCS such as centralized, string, and module integrated converter (MIC) topologies. Among the various types of the DPP systems, the feed-forward method has been selected for both its voltage balancing and power transfer to a modified H-bridge inverter that needs charge balancing of the input capacitors. The modified H-bridge multi-level inverter had some advantages such as a low part count and cost competitiveness when compared to conventional multi-level inverters. Therefore, it is frequently used in photovoltaic (PV) power conditioning system (PCS). However, its simplified switching network draws input current asymmetrically. Therefore, input capacitors in series suffer from a problem due to a charge imbalance. This paper validates the operating principle and feasibility of the proposed topology through the simulation and experimental results. They show that the input-capacitor voltages maintain the voltage balance with the PV MPPT control operating with a 140-W hardware prototype.

• Journal of the Korea Society of Computer and Information
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• v.13 no.7
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• pp.91-98
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• 2008

In digital broadcasting, it is possible to multiplex maximum one hundred audio or music programs into MPEG-2 transport stream, which is suitable for transmitting through one channel. In order to check if multiplex music programs are transmitted well, we need a multiplex audio monitoring system that monitors the programs in real-time. In analog broadcasting, we have used hardware-based audio monitoring system for a small number music programs. However, the effectiveness of hardware-based audio monitoring system from the cost and function viewpoint is so low that a new system is needed for digital broadcasting. In this paper, we have designed and implemented a software-based audio monitoring system to satisfy these requirements. In this implementation, only one PC is used without other hardware facilities, and the system monitors digital broadcasting music programs effectively. Transmitted digital broadcasting streams are demultiplexed into many music programs and the realtime value of audio level and packet error information for these programs are displayed in the screen. Thus, the system detects and shows the abnormal transmitting programs automatically. Simulation results show that effective realtime multiplex audio monitoring is possible for digital broadcasting music programs.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.4
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• pp.211-221
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• 2012

The development of wireless sensor networks (WSNs) is progressed slowly due to limited resources, but it is in progress to the development of the latest IP-based IP-WSN by the development of hardware and power management technology. IPv6 over Low power WPAN (6LoWPAN) is capable of IPv6-built low-power devices. In these IP-based WSNs, existing IP-based techniques which was impossible in WSNs becomes possible. 6LoWPAN is based on the IEEE 802.15.4 sensor networks and is a IPv6-supported technology. Host-based mobility management scheme in IP-WSNs are not suitable due to the additional signaling, network-based mobility management scheme is more suitable. In this paper, we propose an enhanced PMIPv6-based route optimization scheme which consider multi-6LoWPAN network environments. All SLMA (Sensor Local Mobility Anchor) of the 6LoWPAN domain are connected with the SPIG (Sensor Proxy Internetworking Gateway) and performs distributed mobility control for the 6LoWPAN-based inter-domain operations. All information of SLMA in 6LoWPAN domain is maintained by SMAG (Sensor Mobile Access Gateway), and then is performed the route optimization quickly. The status information of the route optimization from SPIG is stored to SLMA and it is supported without additional signaling.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.237-243
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• 2007

In this paper, we propose the Real-time Dead-Pixel Detection and Compensation System for mobile camera and its hardware architecture. The CMOS image sensors as image input devices are becoming popular due to the demand for miniaturized, low-power and cost-effective imaging systems. However a conventional Dead-Pixel Detection Algorithm is disable to detect neighboring dead pixels and it degrades image quality by wrong detection and compensation. To detect dead pixels the proposed system is classifying dead pixels into Hot pixel and Cold pixel. Also, the proposed algorithm is processing line-detector and $5{\times}5$ window-detector consecutively. The line-detector and window-detector can search dead pixels by using one-dimensional(only horizontal) method in low frequency area and two-dimensional(vertical and diagonal) method in high frequency area, respectively. The experimental result shows that it can detect 99% of dead pixels. It was designed in Verilog hardware description language and total gate count is 23K using TSMC 0.25um ASIC library.