• Title/Summary/Keyword: Low-IF

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Low IF Resistive FET Mixer for the 4-Ch DBF Receiver with LNA (LNA를 포함하는 4채널 DBF 수신기용 Low IF Resistive FET 믹서)

  • 민경식;고지원;박진생
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2002.11a
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    • pp.16-20
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    • 2002
  • This paper describes the resistive FET mixer with low IF for the 4-Ch DBF(Digital Beam Forming) receiver with LNA(Low Noise Amplifier). This DBF receiver based on the direct conversion method is generally suitable for high-speed wireless mobile communications. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(IF) considered in this research are 2.09 ㎓, 2.08 ㎓ and 10㎒, respectively. The RF input power, LO input power and Vgs are used -10㏈m, 6㏈m and -0.4 V, respectively. In the 4-Ch resistive FET mixer with LNA, the measured IF and harmonic components of 10㎒, 20㎒, 2.09㎓ and 4.17㎓ are about -12.5 ㏈m, -57㏈m, -40㏈m and -54㏈m, respectively. The IF output power observed at each channel of 10㎒ is about -12.5㏈m and it is higher 27.5 ㏈m than the maximum harmonic component of 2.09㎓. Each IF output spectrum of the 4-Ch is observed almost same value and it shows a good agreement with the prediction.

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Low-Power Block Filtering Architecture for Digital IF Down Sampler and Up Sampler (디지털 IF 다운 샘플러와 업 샘플러의 저전력 블록 필터링 아키텍처)

  • 장영범;김낙명
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.5A
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    • pp.743-750
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    • 2000
  • In this paper, low-power block filtering architecture for digital If down sampler and up sampler is proposed. Software radio technology requires low power and cost effective digital If down and up sampler. Digital If down sampler and up sampler are accompanied with decimation filter and interpolation filter, respectively. In the proposed down sampler architecture, it is shown that the parallel and low-speed processing architecture can be produced by cancellation of inherent up sampler of block filter and down sampler. Proposed up sampler also utilizes cancellation of up sampler and inherent down sampler of block filtering structure. The proposed architecture is compared with the conventional polyphase architecture.

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Design for the Low If Resistive FET Mixer for the 4-Ch DBF Receiver

  • Ko, Jee-Won;Min, Kyeong-Sik;Arai, Hiroyuki
    • Journal of electromagnetic engineering and science
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    • v.2 no.2
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    • pp.117-123
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    • 2002
  • This paper describes the design for the resistive FET mixer with low If for the 4-Ch DBF(Digital Beam Forming) receiver This DBF receiver based on the direct conversion method is generally suitable for high-speed wireless mobile communications. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(If) considered in this research are 2.09 GHz, 2.08 CHz and 10 MHz, respectively. This mixer is composed of band pass filter, a low pass filter and a DC bias circuit. Super low noise HJ FET of NE3210S01 is considered in design. The RE input power, LO input power and Vcs are used -10 dBm, 6 dBm and -0.4 V, respectively. In the 4-Ch resistive FET mixer, the measured If and harmonic components of 10 MHe, 20 MHz and 2.087 CHz are about -19.2 dBm, -66 dBm and -48 dBm, respectively The If output power observed at each channel of 10 MHz is about -19.2 dBm and it is higher 28.8 dBm than the maximum harmonic component of 2.087 CHz. Each If output spectrum of the 4-Ch is observed almost same value and it shows a good agreement with the prediction.

Low Complexity LDPC Encoder (저 복잡도 LPDC 부호화기)

  • Jiang, Xueqin;Lee, Moon-Ho
    • Proceedings of the KIEE Conference
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    • 2007.04a
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    • pp.252-254
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    • 2007
  • In this paper, we will introduce an encoding algorithm of LDPC Codes in Direct-Sequence UWB systems. We evaluate the performance of the coded systems in an AWGN channel. This new algorithm is based on the Jacket matrics. Mathematically let A = ($a_{kl}$) be a matnx, if $A^{-1}$ = $(a^{-1}_{kl})^r$,then the matrix A is a Jacket matrix. If the Jacket matrices if Low density, the inverse matrices is also Low density which is very important to the introduced encoding algorithm.

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Single-Balanced Low IF Resistive FET Mixer for the DBF Receiver

  • Ko Jee-Won;Min Kyeong-Sik
    • Journal of electromagnetic engineering and science
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    • v.4 no.4
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    • pp.143-149
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    • 2004
  • This paper describes characteristics of the single-balanced low IF resistive FET mixer for the digital beam forming(DBF) receiver. This DBF receiver based on the direct conversion method is designed with Low IF I and Q channel. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(IF) considered in this research are 1950 MHz, 1940 MHz and 10 MHz, respectively. Super low noise HJ FET of NE3210S01 is considered in design. The measured results of the proposed mixer are observed IF output power of -22.8 dBm without spurious signal at 10 MHz, conversion loss of -12.8 dB, isolation characteristics of -20 dB below, 1 dB gain compression point(PldB) of -3.9 dBm, input third order intercept point(IIP3) of 20 dBm, output third order intercept point(OIP3) of 4 dBm and dynamic range of 30 dBm. The proposed mixer has 1.0 dB higher IIP3 than previously published single-balanced resistive and GaAs FET mixers, and has 3.0 dB higher IIP3 and 4.3 dB higher PldB than CMOS mixers. This mixer was fabricated on 0.7874 mm thick microstrip $substrate(\varepsilon_r=2.5)$ and the total size is $123.1\;mm\times107.6\;mm$.

A Study on Adaptive Processing of Digital Receiver for Adaptive Array Antenna (어댑티브 어레이 안테나용 디지털 수신기의 적응처리에 관한 연구)

  • 민경식;박철근
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.4
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    • pp.879-885
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    • 2004
  • This paper describes an adaptive signal processing of digital receiver with digital down convertor(DDC). DDC is composed of numerically controlled oscillator(NCO) and digital low pass filler and the received signal is processed by numerical algorithm. The simulation results of digital receiver using the passband sampling technique are presented and we confirmed that the received low IF signal is converted to zero IF by numerically processed DDC. Direction of arrival(DOA) estimation technique using multiple signal classification(MUSIC) algorithm with high resolution is also discussed. We knew that an accurate resolution of DOA depends on the input sampling numbers and antenna element numbers.

CMOS Front-End for a 5 GHz Wireless LAN Receiver (5 GHz 무선랜용 수신기의 설계)

  • Lee, Hye-Young;Yu, Sang-Dae;Lee, Ju-Sang
    • Proceedings of the KIEE Conference
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    • 2003.11c
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    • pp.894-897
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    • 2003
  • Recently, the rapid growth of mobile radio system has led to an increasing demand of low-cost high performance communication IC's. In this paper, we have designed RF front end for wireless LAN receiver employ zero-IF architecture. A low-noise amplifier (LNA) and double-balanced mixer is included in a front end. The zero-IF architecture is easy to integrate and good for low power consumption, so that is coincided to requirement of wireless LAN. But the zero-IF architecture has a serious problem of large offset. Image-reject mixer is a good structure to solve offset problem. Using offset compensation circuit is good structure, too. The front end is implemented in 0.25 ${\mu}m$ CMOS technology. The front end has a noise figure of 5.6 dB, a power consumption of 16 mW and total gain of 22 dB.

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The Analysis of Prescription Used for Low Back Pain in the Yomun(腰門) Chapter of 《Donguibogam(東醫寶鑑)》 (동의보감(東醫寶鑑) 요문(腰門)의 요통처방(腰痛處方)에 대(對)한 분석(分析))

  • An, Jung-Hyeok;Lee, Myung-Jong
    • Journal of Korean Medicine Rehabilitation
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    • v.15 no.1
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    • pp.77-87
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    • 2005
  • Objectives: This analysis of prescription used for low back pain in the Yomun(腰門) chapter of ${\ll}$Donguibogam(東醫寶鑑); The Precious Mirror of Oriental Medicine${\gg}$ is designed to be helpful to practical use of clinics. Methods : Proscriptions used for low back pain in the Yomun(腰門) chapter of ${\ll}$Donguibogam(東醫寶鑑)${\gg}$ were classified and analyzed according to the frequency of proscriptions and the characteristics of each herbs in proscriptions(efficacy, used frequency, related organs etc.) Results and conclusions : After analysis, we obtained the following results : 1. The causes of low back pain are mainly eohyeol(瘀血), yangheo(陽虛), punghanseub(風寒濕). In care of low back pain, I suppose more efficiency that if Angelica gigas NAKAI(當歸) Cnidium officinale MAKINO(三芎) Prunus persica BATSCH(桃仁) is added when the cause is eohyeol(瘀血), or if Psoralea corylifolia L.(破古紙), Cinnamomum cassia PRESL(肉桂), Foeniculum vulare MILL(茴香), Eucommia ulmoides OLIV.(杜冲), Citrus unshiu MARKOVICH(陳皮) are added when the cause is yangheo(陽虛), or if Phellodendron amurense RUPR.(黃柏), Notopterygium incisum TING(羌活), Atractylodes Japonica KOIDZ.(蒼朮) are added when the cause is punghanseub(風寒濕).

Construction and Characterization of Vector Expressing Low Level of Translation Factor eIF5B (단백질합성인자 eIF5B의 저 발현 효모벡터의 제조 및 특성)

  • 최상기;송진희;이준행;이병욱;성치남
    • Korean Journal of Microbiology
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    • v.40 no.1
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    • pp.7-11
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    • 2004
  • eIF5B is a translation initiation factor that delivers Met-$tRNA^{Met}$ to AUG start codon and subsequently joins the small and large ribosomes. In order to study the function of eIF5B encoded by FUN12, we constructed FUN12 which lacked 5' end of its sequence. We found that this construct lacking almost all of its promoter in pRS plasmid partially complemented slow growth phenotype of fun12 deletion strain. Interestingly, this construct expressed N-terminally truncated eIF5B and its expression level was about 5% of that of wild type eIF5B. Low amount of the eIF5B expressed additionally in fun12 deletion strain played a direct role as a limiting factor for its growth. This limiting factor eIF5B in those strains also modulates activities of overall translation in vitro.

A High Swing Range, High Bandwidth CMOS PGA and ADC for IF QPSK Receiver Using 1.8V Supply

  • Lee, Woo-Yol;Lim, Jong-Chul;Park, Hee-Won;Hong, Kuk-Tae;Lee, Hyeong-Soo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.4
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    • pp.276-281
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    • 2005
  • This paper presents a low voltage operating IF QPSK receiver block which is consisted of programmable gain amplifier (PGA) and analog to digital converter. This PGA has 6 bit control and 250MHz bandwidth, $0{\sim}20\;dB$ gain range. Using the proposed PGA architecture (low distortion gain control switch block), we can process the continuous fully differential $0.2{\sim}2.5Vpp$ input/output range and 44MHz carrier with 2 MHz bandwidth signal at 1.8V supply voltage. Using the sub-sampling technique (input freq. is $44{\sim}46MHz$, sampling freq. is 25MHz), we can process the IF QPSK signal ($44{\sim}46MHz$) which is the output of the 6 bit PGA. We can get the SNDR 35dB, which is the result of PGA and ADC at full gain mode. We fabricated the PGA and ADC and the digital signal processing block of the IF QPSK with the 0.18um CMOS MIM process 1.8V Supply.