• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.1
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• pp.117-124
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• 2012

In this paper, we propose a simple H parity check matrix from the CPM(circulant permutation matrix), which can easily avoid the cycle-4, and approach to flexible code rates and lengths. As a result, the operations of the submatrices will become the multiplications between several CPMs, the calculations of the LDPC(low density parity check) encoding could be simplest. Also we consider the fast encoding problem for LDPC codes. The proposed constructions could lead to fast encoding based on the simplest matrices operations for both regular and irregular LDPC codes.

• Smart Media Journal
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• v.2 no.2
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• pp.39-43
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• 2013

In this paper, we suggest a new technique for WPC parity-check matrix (H-matrix) generation and a corresponding decoding process. The key idea is to construct WPC H-matrix by using a convolutional encoder. It is easy to have many different coderates from a mother code with convolutional codes. However, it is difficult to have many different coderates with LDPC codes. Constructing LDPC Hmatrix based on a convolutional code can easily bring the advantage of convolutional codes to have different coderates. Moreover, both LDPC and convolutional decoding algorithms can be applied altogether in the decoding part. This process prevents the performance degradation of short-length WPC code.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.3
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• pp.68-73
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• 2007

Recently, WSN(wireless sensor networks) consists of several sensor nodes in sensor field. And each sensors have the enforced energy constraint. Therefore, it is important to manage energy efficiently. In WSN application system, FEC(Forward error correction) increases the energy efficiency and data reliability of the data transmission. LDPC(Low density parity check) code is one of the FEC code. It needs more encoding operation than other FEC code by growing codeword length. But this code can approach the Shannon capacity limit and it is also can be used to increase the data reliability and decrease the transmission energy. In this paper, the author adopt Linear-Congruence method at generating parity check matrix of LDPC(Low density parity check) codes to reduce the complexity of encoding process and to enhance the energy efficiency in the WSN. As a result, the proposed algorithm can increase the encoding energy efficiency and the data reliability.

• Journal of Broadcast Engineering
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• v.17 no.1
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• pp.122-128
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• 2012

Because of the system delay caused by the number of feedback retransmission in Distributed Video Coding (DVC) scheme, it is difficult to realize practical DVC in many cases. In this paper low feedback retransmission Distributed Source Coding (DSC) scheme is proposed for practical DVC scheme based on Low-Density Parity-Check (LDPC) codes because DVC system is an specific application of DSC system. This DSC scheme is achieved by using different LDPC codes optimized in each different compression rate and using source revealing scheme. Optimized LDPC codes provide us much better decoding performance which causes the 57% reduced number of iteration. Consequently, the number of feedback retransmission is decreased by 50%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.50-57
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• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and compared with the previous results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5C
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• pp.432-438
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• 2010

In this paper we study the effect of bit-to-symbol mappings on the convergence behavior of turbo equalizers employing low-density parity-check (LDPC) codes over high order modulations. We analyze the effective SNR of the outputs from linear minimum mean-squared error (MMSE) equalizers and the convergence property of LDPC decoding for different symbol mappings. Numerical results show that the bit-reliability (BR) mapping provides better performance than random mapping in LDPC-coded turbo equalizers over high order modulations. We also verify the effect of symbol mappings through the noise threshold and error performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2B
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• pp.325-333
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• 2010

Most communication systems including Wibro use quasi-cyclic LDPC codes composed of circulants. However, it is very difficult to design quasi-cyclic(QC) LDPC codes with optimal degree distribution satisfying conditions on layered decoding and girth due to the restriction of the size of its base matrix. In this paper, we propose a good solution by introducing superposition matrices to QC LDPC codes. We derive the conditions on checking girth of QC LDPC codes with superposition matrices, and propose new decoder to support layered decoding both for original QC LDPC codes and their modifications with superposition matrices. Simulation results show considerable improvements to convergence speed and error-correcting performance of proposed scheme which adopts QC LDPC codes with superposition matrices.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.999-1000
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• 2006

The LDPC Code is focusing a powerful FEC(Forward Error Correction) codes for 4G Mobile Communication system. LDPC codes are used minimizing channel errors by modeling AWGN Channel as VDSL system. The performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. LDPC code are encoded by sparse parity check matrix. there are decoding algorithms for a LDPC code, Bit Flipping, Message passing, Sum-Product. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11C
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• pp.901-906
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• 2010

Low density parity check (LDPC) code, first introduced by Gallager and re-discovered by MacKay et al, has attracted researcher's interest mainly due to their performance and low decoding complexity. It was remarkable that the performance is very close to Shannon capacity limit under the assumption of having long codeword length and iterative decoder. However, comparing to turbo codes widely used in the current mobile communication, the encoding complexity of LDPC codes has been regarded as the drawback. This paper proposes a solution for DVB-S2 LDPC encoder to reduce the encoder latency. We use the fast IRA encoder that use the transformation of the parity check matrix into block-wise form and the partial parallel process to reduce the number of system clocks for the IRA code encoding. We compare the proposed encoder with the current DVB-S2 encoder to show that the performance of proposal is better than that of the current DVB-S2 encoder.

• Journal of Communications and Networks
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• v.17 no.3
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• pp.213-220
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• 2015

In this paper, we present a reliability-based iterative proportionality-logic decoding algorithm for two classes of structured low-density parity-check (LDPC) codes. The main contributions of this paper include: 1) Syndrome messages instead of extrinsic messages are processed and exchanged between variable nodes and check nodes, which can reduce the decoding complexity; 2) a more flexible decision mechanism is developed in which the decision threshold can be self-adjusted during the iterative process. Such decision mechanism is particularly effective for decoding the majority-logic decodable codes; 3) only part of the variable nodes satisfying the pre-designed criterion are involved for the presented algorithm, which is in the proportionality-logic sense and can further reduce the computational complexity. Simulation results show that, when combined with factor correction techniques and appropriate proportionality parameter, the presented algorithm performs well and can achieve fast decoding convergence rate while maintaining relative low decoding complexity, especially for small quantized levels (3-4 bits). The presented algorithm provides a candidate for those application scenarios where the memory load and the energy consumption are extremely constrained.