• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.50 no.12
• /
• pp.601-608
• /
• 2001

The ever increasing density of adjustable speed drives(ASD) device with non-linear operating characteristics has been to put tremendous harmonic stress on end user's electrical application. All ASD controllers which employ solid state power devices cause harmonic currents in the source side line. This paper describes harmonic problems for use of ASD. In order to investigate the effect of harmonics caused by using of nonlinear load at the low voltage system, we fixed up simple load model and measured the voltage and current waveforms. Measurement results show that additional operation of linear load at the parallel bus with nonlinear load such as ASD is helpful to the reduction of harmonic influence.

• Proceedings of the KIEE Conference
• /
• 2001.07e
• /
• pp.13-16
• /
• 2001

This paper describes the problems associated with the use of PWM ASDs to drive induction motors. A major effect of harmonic voltages and currents in induction motors is increased heating due to iron and copper losses at harmonic frequencies. The harmonic components thus affect the motor efficiency, and can also affect the torque developed. In order to investigate the effect of harmonics which is caused by using of nonlinear load at the low voltage system, we fixed up simple load model and measured the voltage and current. Measurement. results show that additional operation of linear load at the parallel bus in using nonlinear load such as ASD is helpful to the reduction of harmonic current.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.65 no.3
• /
• pp.178-182
• /
• 2016

FIDVR(Fault Induced Delayed Voltage Recovery) is a phenomenon that recovery of the system voltage level delays after the fault. Cause of FIDVR phenomenon is motor load characteristic about voltage and reactive power. In low voltage condition, the motor go to stall state that consume large amount of reactive power. As a result, the voltage recovery problem is that of repeated occurrences of sustained low voltage following faults on the system. In this paper, analysis the characteristics of the motor load. And using the korean power system actual data, perform a case studies to voltage delay recovery phenomenon alleviation method. Change of each parameters by analyzing the effect on system and selecting an influence parameter. In addition, dynamic characteristic analysis of the resulting difference in the proportion by the motor load in power systems, considering the effect on the voltage stability.

• ETRI Journal
• /
• v.45 no.3
• /
• pp.433-447
• /
• 2023

Critical issues such as connection congestion, long transmission delay, and packet loss become even worse during epidemic, disaster, and so on. In this study, a link load balancing method is proposed to address these issues on the data plane, a plane of the software-defined network (SDN) architecture. These problems are NP-complete, so a meta-heuristic approach, discrete particle swarm optimization, is used with a novel hybrid cost function. The superiority of the proposed method over existing methods in the literature is that it provides link and switch load balancing simultaneously. The goal is to choose a path that minimizes the connection load between the source and destination in multipath SDNs. Furthermore, the proposed work is dynamic, so selected paths are regularly updated. Simulation results prove that with the proposed method, streams reach the target with minimum time, no loss, low power consumption, and low memory usage.

• Journal of Power Electronics
• /
• v.14 no.1
• /
• pp.61-73
• /
• 2014

Multiphase machines are characterized by high power density, enhanced fault-tolerant capacity, and low torque pulsation. For a voltage source inverter supplied multiphase machine, the probability of load imbalances becomes greater and unwanted low-order stator voltage harmonics occur. This paper deals with the PWM control of multiphase inverters under unbalanced load conditions and it proposes a novel near-five-vector SVPWM algorithm based on the five-phase six-leg inverter. The proposed algorithm can output symmetrical phase voltages under unbalanced load conditions, which is not possible for the conventional SVPWM algorithms based on the five-phase five-leg inverters. The cause of extra harmonics in the phase voltages is analyzed, and an xy coordinate system orthogonal to the ${\alpha}{\beta}z$ coordinate system is introduced to eliminate low-order harmonics in the output phase voltages. Moreover, the digital implementation of the near-five-vector SVPWM algorithm is discussed, and the optimal approach with reduced complexity and low execution time is elaborated. A comparison of the proposed algorithm and other existing PWM algorithms is provided, and the pros and cons of the proposed algorithm are concluded. Simulation and experimental results are also given. It is shown that the proposed algorithm works well under unbalanced load conditions. However, its maximum modulation index is reduced by 5.15% in the linear modulation region, and its algorithm complexity and memory requirement increase. The basic principle in this paper can be easily extended to other inverters with different phase numbers.

• Journal of the Korean Solar Energy Society
• /
• v.31 no.6
• /
• pp.95-102
• /
• 2011

The purpose of study is to estimate heating, cooling load performance and economic efficiency in office building with applied the functional paint. this paint can reduced SHGC(Solar Heat Gain Coefficient) on the glazing surface by coating. In this study, estimated to compared with double glazing, low-e glazing, IP(Insulation Paint) and IPu(Insulation UV-Cut Paint) coating glazing. As a result of this study, 1)heating & cooling load Analysis, SHGC value and U-factor of double glazing is about 0.70 and 3.29($W/m^2K$). low-E glazing is about 0.65 and 2.70($W/m^2K$). Two-side it is about 0.27 and 3.25($W/m^2K$). When compared to double glazing, annual heating & cooling load of low-E glazing, Two-side IPu and IP paint coating glazing is 3,012MWh($124kWh/m^2$), 2,910MWh($120kWh/m^2$), 2,867MWh($118.4kWh/m^2$) and 2,867MWh($118.4kWh/m^2$). It i sreduced to 2.0%, 5.2%, 6.7%, and 6.7% respectively. 2)the estimation of economic efficiency, low-e glazing installed in office building can not recover the investment within a lifetime 40years. but IPu and IP paint, two-side coating in glazing, have a payback period of 13 years respectively.

• KSCE Journal of Civil and Environmental Engineering Research
• /
• v.28 no.3D
• /
• pp.399-405
• /
• 2008

Development of the paved track is required as a low-maintenance of conventional line. The paved tracks are one of the types of the ballast reinforced tracks those are manufactured by adopting the prepacked concrete technique. The main elements of this tracks are large sleeper, low elastic pad, fastener, cement mortar, geotextile and recycled ballast. Low elastic pad is the most effective element of such tracks on the basis of stress-displacement characteristics, dynamic response and fatigue characteristics. The stiffness of the pad determine the stiffness of the track. Consequently, it is more important in case of concrete track structure such as paved track because application of low elastic pad seriously effect the durability and stability of the track. The main objective of this study is to confirm the reduction of train load, which transfer to roadbed through various pad effects. To achieve this task static, numerical analysis and real scale repeated loading test was performed while load reduction effect of low elastic pad was analyzed by using displacement, stress and strain ratio characteristics of the paved track.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.28 no.6
• /
• pp.113-121
• /
• 2014

At the end of the 19th century, a battle known as the War of the Currents was fought over how electricity would be generated, delivered, and utilized. In this day and age, there has been a growing interest in Green Growth policies as countermeasures against global warming. As a result of these policies, the use of new and renewable energy needed a power converter to replace fossil fuels has expanded. To reduce power consumption through high efficiency of conversion, Low Voltage DC (LVDC) distribution systems are suggested as an alternative. In a DC distribution system, DC loads are very efficient due to decrease the stages of power conversion. If the LVDC distribution system is adopted, not only DC load but also existing AC loads should be connected with LVDC system. Thus, the modeling of two loads is needed to analyze the DC distribution system. This paper, especially, is focused on the modeling of resistive load and electronic load including power electronic converters using ElectroMagnetic Transient Program (EMTP) software.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.57 no.9
• /
• pp.1516-1521
• /
• 2008

Recently, distribution load analysis using AMR (Automatic Meter Reading) data is researched in electric utilities. Load analysis method based on AMR system generates the typical load profile using load data of AMR customers, estimates the load profile of non-AMR customers, and analyzes the peak load and load profile of the distribution circuits and sectors per every 15 minutes/hour/day/week/month. Typical load profile is generated by the algorithm calculating the average amount of power consumption of each groups having similar load patterns. Traditional customer clustering mechanism uses only contract type code as a key. This mechanism has low accuracy because many customers having same contract code have different load patterns. In this research, We propose a customer clustring mechanism using k-means algorithm with contract type code and AMR data.

• ETRI Journal
• /
• v.32 no.4
• /
• pp.520-529
• /
• 2010

In this paper, we present a low-voltage low-dropout voltage regulator (LDO) for a system-on-chip (SoC) application which, exploiting the multiplication of the Miller effect through the use of a current amplifier, is frequency compensated up to 1-nF capacitive load. The topology and the strategy adopted to design the LDO and the related compensation frequency network are described in detail. The LDO works with a supply voltage as low as 1.2 V and provides a maximum load current of 50 mA with a drop-out voltage of 200 mV: the total integrated compensation capacitance is about 40 pF. Measurement results as well as comparison with other SoC LDOs demonstrate the advantage of the proposed topology.