• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1476-1478
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• 2002

In recent years, the tantalum nitride(TaN) thin-film has been developed for the electronic resistor, inductor and capacitor. In this papers, this study presents the surface profile and sheet-resistance property relationship of reactive-sputtered TaN thin film resistor processed by TaN(tantalum nitride) on alumina substrate. The TCR properties of the TaN films were discussed in terms of crystallization and thin films surface morphology due to annealing temperature. It is clear that the TaN thin-films resistor electrical properties are low TCR related with it's annealing temperature and ambient annealing condition. Respectively, at $300{\sim}400^{\circ}C$ on vacuum and nitrogen annealed thin film resistor having a goof thermal stability and lower TCR properties then as deposited thin films expected for the application to the dielectric material of passive component.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.12
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• pp.48-53
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• 2011

Polymer thin films were prepared by capacitively coupled plasma polymerization process for application of gate insulator. The polymer thin films revealed to form polymer layers with original properties of the monomer. Among the plasma polymer thin films, the styrene polymer having large number of phenyl sites revealed higher dielectric constant of k=3.7 than that of conventional polymer. The plasma polymerized styrene thin film revealed no hysteresis characteristics and low leakage current density of $1{\times}10^{-8}[Acm^{-2}]$ at field strength of $1[MVcm^{-1}]$, which measured by I-V and C-V measurements using MIM and MIS devices.

• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.187-189
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• 2015

A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×10⁵ and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm²/V·s at a drain voltage of −1 V, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.9-12
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• 2004

This paper investigated the stability of Ta-Mo alloy on thin gate dielectric. Ta-Mo alloy was deposited by using co-sputtering process after thermal growing of 3.4nm and 4.2nm silicon dioxide. When the sputtering power of Ta and Mo were 100W and 70W, respectively, the suitable work function for NMOS gate electrode, 4.2eV, could obtain. To prove interface thermal stability of thin film gate dielectric and Ta-Mo alloy, rapid thermal annealing was performed at $600^{\circ}C$ and $700^{\circ}C$ for 10sec in Ar ambient. The results of interface reaction were surveyed by change of silicon dioxide thickness and work function after annealing process. Also, the reliability of alloy gate and gate dielectric could be confirmed by quantity of leakage current. Ta-Mo alloy was showed low sheet resistance and thermal stability, namely, little change of gate dielectric and work function, after $700^{\circ}C$ annealing process.

• ETRI Journal
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• v.31 no.6
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• pp.660-666
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• 2009

We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top-gate In-Ga-Zn-oxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below $200^{\circ}C$, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as $Si_3N_4$ and $Al_2O_3$, the electrical properties are analyzed. After post-annealing at $200^{\circ}C$ for 1 hour in an $O_2$ ambient, the sub-threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative-bias stress tests on TFTs with a $Si_3N_4$ IDL, the degradation sources are closely related to unstable bond states, such as Si-based broken bonds and hydrogen-based bonds. From constant-current stress tests of $I_d$ = 3 ${\mu}A$, an IGZO-TFT with heat-treated $Si_3N_4$ IDL shows a good stability performance, which is attributed to the compensation effect of the original charge-injection and electron-trapping behavior.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.6
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• pp.44-51
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• 1999

The electrical conduction mechanism of high dielectric $(Ba,Sr)TiO_3$ (BST) thin film capacitor, which is the promising cell capacitor for high density DRAM, was investigated in low field region (<0.2MV/cm). It is known that the current in the low field region consists of dielectric relaxation current and leakage current. The current-time (I-t) measurement technique under the constant voltage was used for extracting successfully each current component. The conduction mechanism of the BST capacitor was deduced from the dependency of the current on the measurement temperature, strength of electric field, the polarity of applied electric field and post annealing process. From these results, it was suggested that the dielectric relaxation current and the leakage current are originated from the redistribution of internally trapped electron by hopping process and Pool-Frenkel conduction mechanism, respectively. It was also concluded that traps causing these two current components are due to oxygen vacancies within the BST film.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.114-118
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• 1989

Due to the increased integration density of VLSI circuits a highly reliable thin oxide film is required to fabricate a small geometry MOS device. The behavior of thermal $SiO_2$ under high electric field and current condition has a major effect on MOS device degration and also the practical use of MOS device under irradiation has cause the degration of thin oxide films. In this paper, in order to evaluate the reliability of thin oxides with no stress applied and stressed by the irradiation under low electric field, the tests of TDDB (Time-dependent-dielectric breakdown) are used. Failure times against electric field are examined and acceleration factor is obtained for each case. Based on the experimental data, breakdown wear out limitation for thin oxide films is characterised.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.965-969
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• 2008

MgO thin film is widely used in PDP panel for protecting the dielectric layer and making firing voltage low. In this paper, the MgO thin film and discharge characteristics was analyzed as hydrogen flow rate increasing. Using hydrogen in deposition chamber makes add delay time of PDP module longer or shorter. It is the reason why thin film surface layer thickness on the MgO surface changes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.510-514
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• 1997

The thin film that is electrically conductive and optically transparent is called conductive transparent thin film. ITO(Indium-Tin Oxide) which is a kind of conductive transparent thin film has been widely used in solar cell, transparent electrical heater, selective optical filter, FDP(Flat Display Panel) such as LCD(Liquid Crystal Display), PDP(Plasma Display Panel) and so on. Especially in PDP, ITO films is used as a transparent electrode in order to maintain discharge and decrease consumption power through the improvement of cell structure. In this study, we prepared ITO by reactive r.f. sputtering with indium-tin(Sn 10wt%) alloy target instead of indium-tin oxide target. The ITO films deposited at low temperature 15$0^{\circ}C$ and 8% $O_2$. Partial pressure showed about 3.6 Ω/$\square$. At the end of firing, the resistance of ITO was decreased, the optical transparence was improved above 90%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.33-36
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• 1999

In this paper, $Ba_{0.5}$Sr$_{0.5}$TiO$_3$ thin-films were prepared on Pt/Ti/Si0$_2$/Si substrates by RF magnetron sp-uttering method. We investigated electric and dielectric properties of BST thin-films with various ann-ealing temperature using in-sute RTA. Deposition conditions of BST films were set substrate temperat-ure, 30$0^{\circ}C$ and working gas ratio, Ar:O$_2$=90:10. After BST films deposited, we fabricated a capacitor of MIM structure with Al top electrode for measurement. Post-annealing using RTA performed at 40$0^{\circ}C$, $600^{\circ}C$, 80$0^{\circ}C$ for 60 sec, respectively. Also we exacted crystallization and composition of BST thin-films by XRD analysis. In measurement result, this capacitors showed a dielectric constant of about 200 at 1MHz and leakage current density of 5$\times$10$^{-8}$ A/$\textrm{cm}^2$ at 1.5V Microstructure of BST thin-films exhibited effective quality in low-temperature annealed 71ms than high-temperature annealed 71ms.s.s.