• The Transactions of the Korean Institute of Power Electronics
• /
• v.18 no.1
• /
• pp.45-53
• /
• 2013

Fuel cell power system is one of the most promising energy source for the alternative energy because it has unique advantages such as high energy density, no power drop during operation, and feasible to make compact size. However, due to very low response time, fuel cell is difficult to correspond to drastic load changes and start-up operation. For solving these problem, fuel cell power system must include energy storage device such as Li-Poly battery or super capacitor. Therefore, bi-directional DC-DC converter must be required for this storage device and fuel cell-PCS control. This paper presents a design and modeling of the bi-directional DC/DC converter. Firstly, we present modeling the boost and buck mode of the bi-directional converter through both PWM switch model and state space averaging technique. Secondly, in order to minimize output ripple and transient response overshoot, we have two identical DC-DC converters interleaved and adopt two-loop voltage-current controller. The proposed bi-directional DC-DC converter's modeling method and control design have been verified with computer simulation and experimentation.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.7 s.361
• /
• pp.7-11
• /
• 2007

This paper presents a multiband octa-phase LC VCO for SDR receiver. Four identical LC VCOs are connected by using series coupling transistor to obtain the octa-phase signal and low phase noise characteristic. For a multiband application, a band tuning circuit that consists of a switch capacitor circuit and two MOS varactors is proposed. As the MOS switch is on/off state, the frequency range will be varied. In addition, two varactors make the VCO be immune to process variation of the oscillation frequency. The VCO is designed in 0.18-um CMOS technology, consumes 12mA current from 1.8V supply voltage and operates with a frequency band from 885MHz to 1.342GHz (41% tuning range). As driving sub-harmonic mixer, the proposed VCO covers 3 standards(CDMA 2000 1x, WCDMA, WiBro). The measured phase noise is -105dBc@100kHz, -115dBc@1MHz, -130dBc@10MHz for CDMA 2000 1x, WCDMA, WiBro respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.24 no.4
• /
• pp.319-324
• /
• 2011

This paper dealt with a partial discharge (PD) detection method for insulation diagnosis in cast-resin transformers. To detect PD pulse, a planar-capacitive probe was designed and fabricated. The probe has no insulation problem and can be installed on cast-resin transformers even in operation since it does not connect with high voltage conductor. The PD measurement system consists of the capacitive probe, a coupling network of 100 [kHz] low-cutoff frequency, and an amplifier with a gain of 40 [dB] and a frequency bandwidth of 500 [Hz]~45 [MHz]. A plane-needle and a plane-plane electrode system were fabricated to simulate insulation defects in a cast-resin transformer. Sensitivity of the PD measurement system, which is evaluated by a standard calibrator was 0.35 [mV/pC] for positive and 0.45 [mV/pC] for negative, respectively. The PD detection by the capacitive probe was less sensitive than that by a coupling capacitor according to IEC 60270, but we could analyze the magnitude and the phase distribution of PD pulse.

• Journal of IKEEE
• /
• v.16 no.4
• /
• pp.335-342
• /
• 2012

This paper is studied on a new DCM-ZVS step up-down AC-DC converter of high performance, that is, high system efficiency and power factor correction (PFC). The switching devices in the proposed converter are operated by soft switching technique using a new quasi-resonant circuit, and are driven with discontinuous conduction mode (DCM) according to pulse width modulation (PWM). The quasi-resonant circuit uses a step up-down inductor and a loss-less snubber capacitor. The proposed converter with DCM also simplifies the requirement of control circuits and reduces the number of control components. The input AC current waveform in the proposed converter becomes a quasi-sinusoidal waveform proportional to the magnitude of input AC voltage under constant switching frequency. As a result, the proposed converter obtains low switching power loss and high efficiency, and its input power factor is nearly in unity. The validity of the analytical findings is confirmed by some computer simulation results and experimental results.

• Bulletin of the Korean Chemical Society
• /
• v.33 no.7
• /
• pp.2207-2212
• /
• 2012

Dimethylaluminum isopropoxide (DMAI, $(CH_3)_2AlO^iPr$) as a single precursor, which contains one aluminum and one oxygen atom, has been adopted to deposit non-stoichiometric aluminum oxide ($AlO_x$) films by low pressure metal organic chemical vapor deposition without an additional oxygen source. The atomic concentration of Al and O in the deposited $AlO_x$ film was measured to be Al:O = ~1:1.1 and any serious interfacial oxide layer between the film and Si substrate was not observed. Gaseous by-products monitored by quadruple mass spectrometry show that ${\beta}$-hydrogen elimination mechanism is mainly contributed to the $AlO_x$ CVD process of DMAI precursor. The current-voltage characteristics of the $AlO_x$ film in Au/$AlO_x$/Ir metalinsulator-metal (MIM) capacitor structure show high ON/OFF ratio larger than ${\sim}10^6$ with SET and RESET voltages of 2.7 and 0.8 V, respectively. Impedance spectra indicate that the switching and memory phenomena are based on the bulk-based origins, presumably the formation and rupture of filaments.

• Transactions on Electrical and Electronic Materials
• /
• v.12 no.6
• /
• pp.262-266
• /
• 2011

A simulation study of a current-mode direct current (DC)-DC boost converter is presented in this paper. This converter, with a fully-integrated power module, is implemented by using bipolar complementary metal-oxide semiconductor (BiCMOS) technology. The current-sensing circuit has an op-amp to achieve high accuracy. With the sense metal-oxide semiconductor field-effect transistor (MOSFET) in the current sensor, the sensed inductor current with the internal ramp signal can be used for feedback control. In addition, BiCMOS technology is applied to the converter, for accurate current sensing and low power consumption. The DC-DC converter is designed with a standard 0.35 ${\mu}m$ BiCMOS process. The off-chip inductor-capacitor (LC) filter is operated with an inductance of 1 mH and a capacitance of 12.5 nF. Simulation results show the high performance of the current-sensing circuit and the validity of the BiCMOS converter. The output voltage is found to be 4.1 V with a ripple ratio of 1.5% at the duty ratio of 0.3. The sensing current is measured to be within 1 mA and follows to fit the order of the aspect ratio, between sensing and power FET.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.12
• /
• pp.53-60
• /
• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.5
• /
• pp.24-32
• /
• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.5
• /
• pp.51-57
• /
• 2015

In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.

• Journal of Sensor Science and Technology
• /
• v.14 no.1
• /
• pp.33-41
• /
• 2005

For more convenient electrode-electrolyte interface impedance analysis in biosensor, a stand-alone impedance measurement system is required. In our study, we developed a PC-based portable system to analyze impedance of the electrochemical cell using microprocessor. The devised system consists of signal generator, programmable amplifiers, A/D converter, low pass filter, potentiostat, I/V converter, microprocessor, and PC interface. As a microprocessor, PIC16F877 which has the processing speed of 5 MIPS was used. For data acquisition, the sampling rate at 40 k samples/sec, resolution of 12 bit is used. RS-232 with 115.2 kbps speed is used for the PC communication. The square wave was used as stimuli signal for impedance analysis and voltage-controlled current measurement method of three-electrode-method were adopted. Acquired voltage and current data are calculated to multifrequency impedance signal after Fourier transform. To evaluate the implemented system, we set up the dummy cell as equivalent circuit of which was composed of resistor, parallel circuit of capacitor and resistor connected in parallel and measured the impedance of the dummy cell; the result showed that there exist accuracy within 5 % errors and reproduction within 1 % errors compared to output of Hioki LCR tester and HP impedance analyzer as a standard product. These results imply that it is possible to analyze electrode-electrolyte interface impedance quantitatively in biosensor and to implement the more portable high speed impedance analysis system compared to existing systems.