• Journal of Power Electronics
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• v.18 no.6
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• pp.1659-1669
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• 2018

An improved circulating current suppression control method is proposed in this paper. In the proposed controller, an outer loop of the average capacitor voltage control model is used to balance the sub-module capacitor voltage. Meanwhile, an individual voltage balance controller and an arm voltage balance controller are also used. The DC and harmonic components of the circulating current are separated using a low pass filter. Therefore, a multiple quasi-proportional-resonant (multi-quasi-PR) controller is introduced in the inner loop to eliminate the circulating harmonic current, which mainly contains second-order harmonic but also contains other high-order harmonics. In addition, the parameters of the multi-quasi-PR controller are designed in the discrete domain and an analysis of the stability characteristic is given in this paper. In addition, a simulation model of a three-phase MMC system is built in order to confirm the correctness and superiority of the proposed controller. Finally, experiment results are presented and compared. These results illustrate that the improved control method has good performance in suppressing circulating harmonic current and in balancing the capacitor voltage.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.61 no.1
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• pp.41-46
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• 2012

Electrolytic power capacitors have been widely used in power conversion system such as inverter or UPS because of characteristics of large capacitance, high-voltage and low-cost. The electrolytic capacitor, which is most of the time affected by the aging effect, plays a very important role for the power-electronics system quality and reliability. Therefore it is important to diagnosis monitoring the condition of an electrolytic capacitor in real-time to predict the failure. In this paper, the on-line remote diagnosis monitoring system for UPS DC link electrolytic capacitors using low-cost single-chip zigbee communication modules is developed. To estimate the health status of the capacitor, the equivalent series resistor(ESR) of the component has to be determined. The capacitor ESR is estimated by using RMS computation using BPF modeling of DC link ripple voltage/current. Zigbee-based hardware experimental results show that the proposed remote capacitor diagnosis monitoring system can be applied to UPS successfully.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.4
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• pp.1-11
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• 1981

This paper proposes a method of generalizing the clocking scheme in the Switched Capacitor Filter(SCF) design using Voltage Inverter Switches (VIS's). Parallel RC and RL elements, and parallel LC resonators can be implemented by the proposed clocking schemes Applying these new elements and the generalized clocking schemes to the SCF design, the total number of required operational amplifiers and capacitors can be reduced. Experimental results of a band- stop filter and a low-pass filter using a new type grounded VIS show good agreements with t he theoretical characteristics.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.216-226
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• 2015

The neutral beam injection generate ultra-high temperature energy in the tokamak of nuclear fusion. The neutral beam injection make up arc power supply, filament power supply and acceleration & deceleration power supply. The arc power supply has characteristics of low voltage and high current. Arc power supply generate arc through constant output of voltage and current. So this paper proposed suitable buck converter for low voltage and high current. The proposed buck converter used parallel switch because it can be increased capacity and decrease conduction loss. When an arc generated, the neutral beam injection chamber occur high voltage. And it will break output capacitor of buck converter. Therefore the output capacitor was removed in the proposed converter. Thus the proposed converter should be designed for the characteristics of low voltage and high current. Also, the arc power supply should be guaranteed for system stability. The proposed parallel buck converter enables the system stability of the divided low output voltage and high current. The proposed converter with constant output be the most important design of the output inductor. In this paper, designed arc power supply verified operation of system and stability through simulation and prototype. After it is applied to the 288[kW] arc power supply for neutral beam injection.

• Journal of Power Electronics
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• v.17 no.1
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• pp.115-126
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• 2017

This paper presents a new cascaded asymmetrical single phase multilevel converter with a reduced number of isolated DC sources and power semiconductor switches. The proposed inverter has only two H-bridges connected in cascade, one switching at a high frequency and the other switching at a low frequency. The Low Switching Frequency Inverter (LSFI) generates seven levels whereas the High Switching Frequency Inverter (HSFI) generates only two levels. This paper also presents a solution to the capacitor balancing issues of the LSFI. The proposed inverter has lot of advantages such as reductions in the number of DC sources, switching losses, power electronic devices, size and cost. The proposed inverter with a capacitor voltage balancing algorithm is simulated using MATLAB/SIMULINK. The switching logic of the proposed inverter with a capacitor voltage balancing algorithm is developed using a FPGA SPATRAN 3A DSP board. A laboratory prototype is built to validate the simulation results.

• Journal of Power Electronics
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• v.17 no.1
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• pp.96-105
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• 2017

In this paper, a hybrid modular multilevel converter (MMC) topology with an improved nearest level modulation method is proposed for medium-voltage high-power applications. The arm of the proposed topology contains N series connected half-bridge submodules (HBSMs), one full-bridge submodule (FBSM) and an inductor. By exploiting the FBSM, half-level voltages are obtained in the arm voltages. Therefore, an output voltage with a 2N+1 level number can be generated. Moreover, the total level number of the inserted submodules (SMs) is a constant. Thus, there is no pulse voltage across the arm inductors, and the SM capacitor voltage is rated. With the proposed voltage balancing method, the capacitor voltage of the HBSM is twice the voltage of the FBSM, and each IGBT of the FBSM has a relatively low switching frequency and an equalized conduction loss. The capacitor voltage balancing methods of the two kinds of SMs are implemented independently. As a result, the switching frequency of the HBSM is not increased compared to the conventional MMC. In addition, according to a theoretical calculation of the total harmonic distortion of the electromotive force (EMF), the voltage quality with the presented method can be significantly enhanced when the SM number is relatively small. Simulation and experimental results obtained with a MMC-based inverter verify the validity of the developed method.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.12
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• pp.584-590
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• 2002

Crowbar system is usually applied to a pulsed power system in which a capacitor bank is discharged into a load. This provides a free wheeling path for the load current and prevents the capacitor from recharging due to a reverse voltage. Usually diodes have been used as a crowbar switch, but it is not a practical system because the cost of the diodes goes up enormously with increasing the system voltage and current. This paper presents a novel protection scheme of a charging and discharging system of a 300 kJ capacitor bank using a low-cost crowbar system which consists of a crowbar switch and resistors. Triggered vacuum switch(TVS) was used for a crowbar switch, and Rogowski coil was used to determine a trigger time of TVS. When this crowbar system is applied to our pulsed power system which consists of capacitor bank($123muF$), inductor() for forming a pulse, load resistor$(100 m\Omega)$, and a closing switch, instantaneous reversal voltage of capacitor bank could be limited less than 1.8 ㎸ until capacitor bank was charred to 17 ㎸.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.56 no.2
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• pp.83-89
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• 2007

The LC filter design procedure of the inverter output filter is described. The transfer function of the filter output voltage to the load current is described with the capacitor value and the system time constant considering the system controller. By using the closed form of the relation between the filter capacitor value and the system time constant, the capacitor value can be calculated with the given system time constant and vice versa. It is more practical for the implementation of power and control circuit of inverter. And as the effect of the load current to the voltage distortion can be calculated from the closed form, it is possible to analyze the system how much the voltage waveform is distorted in case of the nonlinear load. All the proposed design procedure is verified with the simulation and experimental results.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• Journal of Industrial Technology
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• v.32 no.A
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• pp.115-118
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• 2012

Recently, there are a lot of papers in order to replace the electrolytic capacitor into the film capacitor in output of PFC(Power Factor Correction). However, the film capacitor, which has capacitance of low values, causes a large ripple voltage in output of PFC. The LED drivers are connected series in the output of PFC and affected by the magnitude of voltage ripple. In this paper, we have compared the fixed frequency method with the variable frequency for the constant-current control and propose the control method to avoid the sub-harmonic oscillation in the variable input voltage. An 80W PFC, using film capacitors instead of electrolytic capacitors, and LED driver has been built and compared the fixed frequency control method with the variable frequency control method.