• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.19-27
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• 2007

This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.

• Korean Journal of Materials Research
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• v.18 no.4
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• pp.169-174
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• 2008

The structural and electrical properties of amorphous $BaSm_2Ti_4O_{12}$ (BSmT) films on a $TiN/SiO_2/Si$ substrate deposited using a RF magnetron sputtering method were investigated. The deposition of BSmT films was carried out at $300^{\circ}C$ in a mixed oxygen and argon ($O_2$ : Ar = 1 : 4) atmosphere with a total pressure of 8.0 mTorr. In particular, a 45 nm-thick amorphous BSmT film exhibited a high capacitance density and low dissipation factor of $7.60\;fF/{\mu}m2$ and 1.3%, respectively, with a dielectric constant of 38 at 100 kHz. Its capacitance showed very little change, even in GHz ranges from 1.0 GHz to 6.0 GHz. The quality factor of the BSmT film was as high as 67 at 6 GHz. The leakage current density of the BSmT film was also very low, at approximately $5.11\;nA/cm^2$ at 2 V; its conduction mechanism was explained by the the Poole-Frenkel emission. The quadratic voltage coefficient of capacitance of the BSmT film was approximately $698\;ppm/V^2$, which is higher than the required value (<$100\;ppm/V^2$) for RF application. This could be reduced by improving the process condition. The temperature coefficient of capacitance of the film was low at nearly $296\;ppm/^{\circ}C$ at 100 kHz. Therefore, amorphous BSmT grown on a TiN substrate is a viable candidate material for a metal-insulator-metal capacitor.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• Journal of the Korean institute of surface engineering
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• v.34 no.5
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• pp.481-485
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• 2001

We investigated the structural and electrical properties of the Ba ($Zr_{x}$ $T_{il-x}$ )$O_3$ (BZT thin films with a mole fraction of x=0.2 and thickness 150 nm for the application in MLCC (Multilayer Ceramic Capacitor). BZT films were prepared on $Pt/SiO_2$/Si substrate at various substrate temperatures by the RF-magnetron sputtering system. When the substrate temperature was above $500^{\circ}C$, we could obtain multi-crystalline BZT films oriented at (110), (111), and (200) directions. The crystallization of the film and high dielectric constant were observed with the increase of substrate temperature. Capacitance of the film deposited at high temperature is more sensitive to the applied voltage than that of the film deposited at low temperature. This paper reports surface morphology, dielectric constant, dissipation factor, and C-V characteristics for BZT films deposited at three different temperatures. The BZT film deposited at 40$0^{\circ}C$ shows stable electrical properties but a little small dielectric constant for MLCC application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.10-10
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• 2009

Transparent BNO thin films were grown on Al-doped ZnO (AZO)/Ag/AZO/polyethersulfon (PES) (abbreviated as AAAP) transparent electrodes at a low temperature by the NCD technique. The BNO films grown on the crystallized AZO/Ag/AZO (AAA) electrodes exhibit an amorphous phase with a root mean square (rms) roughness of approximately 2 nm in the range of deposition temperature. The capacitors (Pt/BNO/AAAP) with BNO films grown at $100^{\circ}C$ show a dielectric constant of 24 and dissipation factor of 8% at 100 kHz, a leakage current density of about $8{\times}10^{-6}A/cm^2$ at an applied voltage of 1.0V. The optical transmittances of the BNO/AAAP exhibited above 80% at wavelength of 550nm at all of deposition temperature. The mechanical stability of the BNO/AAA as well as AAA electrode with the PES substrates through the bending was ensured for flexible electronic device applications. The transparent BNO capacitors grown on AAAP are powerful candidate for integration with the transparent solar cells.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.1
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• pp.44-50
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• 2015

This paper presents a high speed synchronous single inductor dual output boost converter using Type-III compensation for power management in smart devices. Maintaining multiple outputs from a single inductor is becoming very important because of inductor the sizes. The uses of high switching frequency, inductor and capacitor sizes are reduced. Owing to synchronous rectification this kind of converter is suitable for SoC. The phase is controlled in time sharing manner for each output. The controller used here is Type-III, which ensures quick settling time and high stability. The outputs are stable within $58{\mu}s$. The simulation results show that the proposed scheme achieves a better overall performance. The input voltage is 1.8V, switching frequency is 5MHz, and the inductor used is 600nH. The output voltages and powers are 2.6V& 3.3V and 147mW &, 230mW respectively.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.183-188
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• 2015

A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is always straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most significant bit (MSB) is decided without any switching power consumption. The application of the straightforward switching causes lower power consumption in the structure. The input is sampled at the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity and a higher effective number of bits. The comparator applies adaptive power control, which reduces the overall power consumption. The differential prototype SAR ADC was implemented with $0.18{\mu}m$ complementary metal-oxide semiconductor (CMOS) technology and achieves an effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95 fJ/conversion-step.

• Proceedings of the KIEE Conference
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• 2008.04c
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• pp.239-241
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• 2008

A powered system with fuel cell is regarded as a high current and low voltage source. Effects of the loads on the electrical power source are important to optimize the integrated power system. The design parameters of the system should be chosen by taking into account the characteristics of the fuel cell, so the costs of the power system at given operating conditions can be reduced. Furthermore, the dynamics characteristic of the system is crucial to acquire performance in applications, particularly interactions between loads and the fuel cell system. Currently, no integrated simulation has been approached to analyze interrelated effects. Therefore, the dynamic models of power conversion system with a PEM fuel cell that includes the PEM fuel cell stack, DC/DC converter and associated controls is developed. Electric lads for the system are derived by using a power theory that separates a load current into active, reactive, distortion or a mixed current component. Dependency of the DC capacitor on the loads are analyzed.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.55 no.1
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• pp.26-30
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• 2006

For the purpose of developing capacitive humidity sensor having interdigital electrodes, interdigital electrode was modeled and simulated to obtain capacitance and sensitivity as a function of geometric parameters like the structural gap and thickness. For the development of ASIC, switched capacitor signal processing circuits for capacitive humidity sensor were designed and simulated by Cadence using $0.25{\mu}m$ CMOS process parameters. The signal processing circuits are composed of amplifier for voltage gain control, and clock generator for sensor driving and switch control. The characteristics of the fabricated sensors are; 1) sensitivity is 9fF/%R.H., 2) temperature coefficient of offset(TCO) is $0.4%R.H./^{\circ}C$, 3) nonlinearity is 1.2%FS, 4) hysteresis is 1.5%FS in humidity range of $3%R.H.{\sim}98%R.H.$. The response time is 50 seconds in adsorption and 70 seconds in desorption. Fabricated process used in this capacitive humidity sensor having interdigital electrode are just as similar as conventional IC process technology. Therefore this can be easily mass produced with low cost, simple circuit and utilized in many applications for both industrial and environmental measurement and control system, such as monitoring system of environment, automobile, displayer, IC process room, and laboratory etc.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1349-1355
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• 2009

This paper is studied on a novel power factor correction (PFC) AC-DC converter of high efficiency by soft switching technique. The input current waveform in the proposed converter is got to be a sinusoidal form composed of many a discontinuous pulse in proportion to the magnitude of a ac input voltage under the constant switching frequency. Therefore, the input power factor is nearly unity and the control method is simple. The proposed converter adding an electric isolation operates with a discontinuous current mode (DCM) of the reactor in order to obtain some merits of simpler control, such as fixed switching frequency, without synchronization control circuit used in continuous current mode (CCM). To achieve the soft switching (ZCS or ZVS) of control devices, the converter is constructed with a new loss-less snubber for a partial resonant circuit. It is that the switching losses are very low and the efficiency of the converter is high, Particularly, the stored energy in a loss-less snubber capacitor recovers into input side and increases input current from a resonant operation. The result is that the input power factor of the proposed converter is higher than that of a conventional PFC converter. This paper deals mainly with the circuit operations, theoretical, simulated and experimental results of the proposed PFC AC-DC converter in comparison with a conventional PFC AC-DC converter.