• Journal of Power Electronics
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• v.17 no.4
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• pp.923-932
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• 2017

This paper proposes a novel scheme which can compensate the common-mode voltage (CMV) for five-level active neutralpoint clamped (5L-ANPC) inverters, which is based on modifying the space vector pulse width modulation (SVPWM) and adding an auxiliary leg to the inverter. For the modified SVPWM, only the 55 voltage vectors producing low CMV values among the 125 possible voltage vectors are utilized, which varies over the three voltage levels of $-V_{dc}/12$, 0 V, and $V_{dc}/12$. In addition, the compensating voltage, which is injected into the 5L-ANPC inverter system to cancel the remaining CVM through a common-mode transformer (CMT) is generated by the additional NPC leg. By the proposed method, the CMV of the inverter is fully eliminated, while the utilization of the DC-link voltage is not decreased at all. Furthermore, all of the DC-link and flying capacitor voltages of the inverter are well controlled. Simulation and experimental results have verified the validity of the proposed scheme.

• International journal of advanced smart convergence
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• v.4 no.1
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• pp.64-70
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• 2015

This paper proposes fluorescent electronic ballast with high power factor and low line input current harmonics. The system performance can be improved by a charged pump circuit. Details of design and circuit operation are described. The proposed electronic ballast is modified from single-stage half bridge class D electronic ballast by adding capacitor parallel with each power switch and setting the circuit parameter to operate under class DE inverter condition. By using this proposed method the DC bus voltage can be reduced around by 50% compare with conventional class D inverter circuit. Because the power switches are operated at zero voltage switching condition and low dv/dt of class DE switching. The experimental results show that the proper frequency of the prototype is around 50 kHz with input power factor of 0.982, $THD_i$ 10.2% at full load and efficiency of more than 90%.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.201-204
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• 2000

In this paper, an A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10Msample/s. This architecture is proposed using the 2-step architecture for high speed conversion rate. It is consisted of sample/hold circuit, low power comparator, voltage reference circuit and DAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.2$\mu\textrm{m}$ CMOS technology. The SNR is 45.3dB at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10Msample/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are ${\pm}$1 / ${\pm}$2 LSB, respectively. The power consumption is 13㎽ at single +2.5V supply voltage.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.561-565
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• 2001

This paper proposes a new switching scheme of a static var compensator(SVC) with cascade multilevel inverter which employs H-bridge inverter(HBI). To improve the un­balanced problem of the DC capacitor voltages, the rotated switching scheme of fundamental frequency is newly used. The optimized fundamental switching pattern with low switching frequency is adapted to be suitable for high application. The selective harmonic elimination method(SHEM) allows to keep the total harmonic distortion(THD) low in the output voltage of multilevel inverter. The SVC system is modeled using the d-q transform which calculates the instantaneous reactive power. This model is used to design a controller and analyze the SVC system. Simulated and experimental results are also presented and discussed to validate the proposed schemes.

• Proceedings of the KIEE Conference
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• 2003.07e
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• pp.144-148
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• 2003

This paper examines the application of high voltage static var compensator(SVC) with cascade multilevel inverter which employs H-bridge inverter(HBI). To improve the unbalanced problem of the DC capacitor voltages, the rotated switching scheme of fundamental frequency is newly used. The optimized fundamental switching pattern with low switching frequency is adapted to be suitable for high application. The selective harmonic elimination method(SHEM) allows to keep the total harmonic distortion(THD) low in the output voltage of multilevel inverter. The SVC system is modeled using the d-q transform which calculates the instantaneous reactive power. This model is used to design a controller and analyze the SVC system. Simulated and experimental results are also presented and discussed to validate the proposed schemes.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.264-269
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• 1998

A proposed soft-switching buck-boost PWM converter has a lot of advantages, Viz., electric isolation, a high power factor, low switching losses, low EMI noise, reduction of the voltage and current stresses, etc. In a new PFC converter, the switching device is replaced by the loss-less snubber circuit to achieve the zero voltage switching (ZVS) at the maximum current. However, the charging current of the capacitor in the loss-less snubber circuit distorts the input current waveforms. To improve the input current waveform, a new duty factor control method is proposed in this paper.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.6
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• pp.542-545
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• 2016

This work proposes a capacitive coupling-based wireless battery charging circuit that is built with vehicle glasses for electric vehicles. A capacitive coupling wireless power transfer offers many advantages, such as low metal impact and low energy transfer efficiency changes in accordance with changes in position. However, a large coupling capacitor is needed for high power transfer. Therefore, a new capacitive coupling-based wireless power transfer LLC resonant converter built with the glasses of an electric vehicle is proposed. The proposed converter is composed of coupling capacitors with glasses of an electric vehicle and two transformers for impedance transformation. The proposed LLC converter can transfer large power and obtain high efficiency with zero voltage switching. The validity and features of the proposed circuit is verified by experimental results with a 1.2 kW prototype.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.627-628
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• 2006

A low-voltage switched-capacitor $2^{nd}$-order $\Sigma\Delta$ modulator using full feed-forward is introduced. It has two advantages: the unity signal transfer function and reduced signal swings inside the $\Sigma\Delta$ loop. These features greatly relax the DC gain and output swing requirements for Op-Amp in the low-voltage $\Sigma\Delta$ modulator. Implemented by a 0.18-${\mu}m$ CMOS technology, the $\Sigma\Delta$ modulator satisfies performance requirements for WCDMA and CDMA2000 standards.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.241-243
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• 2007

Two-stage charge equalization scheme for HEV lithium-ion battery string is proposed with the optimal power rating design rule in this paper, where in the first stage the over charged energy of higher voltage cells is drawn out to the single common output capacitor and then, that discharged energy is recovered into the overall battery stack in the second stage. To achieve charge equalization of sort, the conventional flyback DC/DC converters of low power and minimized size are employed. The industrial sample employing both the proposed two-stage cell balancing scheme and the optimal power rating design rule shows good cell balancing performance with reduced size as well as low voltage stresses of the electronic devices.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.238-240
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• 2007

A new ZVZCS Single-Stage Power-Factor-Correction(PFC) AC/DC converter with boost PFC cell is integrated with voltage doubler rectified asymmetrical half-bridge(VDRAHB) is proposed in this paper. The proposed converter features good power factor correction, low current harmonic distortions, tight output regulations and low voltage of link capacitor. An 85W prototype was implemented to show that it meets the harmonic requirements and standards satisfactorily with nearly unity power factor and high efficiency over universal input.