• 전기학회논문지P
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• 제52권4호
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• pp.148-153
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• 2003

In this paper, the low voltage 3V Sigma-Delta Digital Analog Converter(DAC) is designed for using in the transmitter of ADSL analog front-end. We have developed the CMOS DAC according to ANSI T1.413-2(DMT) standard specifications of the chip. The designed 4th-order DAC is composed of three block which are 1-bit DAC, 1st-order Switched-Capacitor filter and analog active 2nd-order Resistor-Capacitor(RC) filter. The HSPICE simulation of the designed DAC showing 65db SNR, is connected with 1.1MHz continuous lowpass filter. And also, we have performed the circuits verification and layout verification(ERC, DRC, LVS) followed by fabrication using TSMC 2-poly 5-metal p-substrate CMOS $0.35{\mu}m$ processing parameter. Finally, the chip testing has been performed and presented in the results.

• Smart Structures and Systems
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• 제26권4호
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• pp.521-531
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• 2020

In this paper, a new interleaved high step-up converter with low voltage stress on the switches is proposed. In the proposed converter, soft switching is provided for all switches by just one auxiliary switch, which decreases the conduction loss of auxiliary circuit. Also, the auxiliary circuit is expanded on the converter with more input branches. In the converter all main switches operate under zero voltage switching condition and auxiliary switch operate under zero current switching condition. Because of the interleaved structure, the reliability of converter increases and input current ripples decreases. The clamp capacitor in the converter not only absorb the voltage spikes across the switch due to leakage inductance, but also improve voltage gain. The proposed converter is fully analyzed and to verify the theoretical analysis, a 100 W prototype was implemented. Also, to show the effectiveness of auxiliary circuit on conduction EMI, EMI of the proposed converter comprised with hard switching counterpart.

• 대한전자공학회논문지SD
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• 제46권1호
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• pp.45-51
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• 2009

심장박동 조절장치를 위한 저전압 저전력 전단 처리기를 제안한다. 제안된 회로는 80 Hz에서 120 Hz의 대역폭을 가지는 4차의 스위치드 커패시터 필터와 0 dB에서 24 dB까지 0.094 dB 간격으로 전압이득의 조절이 가능한 전압증폭기를 구현하였다. 낮은 전압에서 동작하고, 전력소모를 극소화하기 위해서 인버터 기반의 스위치드 커패시터 회로를 사용하였으며, 인버터가 가지는 작은 전압이득을 보상하기 위해서 상호상관 기법을 사용하였다. 제안된 회로는 $0.35-{\mu}m$ CMOS 공정을 이용하여 구현되었으며, 5kHz의 샘플링 주파수에서 80-dB의 SFDR을 가진다. 이때 전력소모는 1 V의 전원전압에서 330 nW에 불과하다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.286-292
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• 2006

This paper presents the design of a low-voltage wide-band switched-capacitor (SC) filter for wireless communication receiver applications. The filter is the 5th-order Elliptic lowpass filter. With the clock frequency of 50MHz implying that an effective sampling frequency is 100MHz with double sampling scheme, the cut-off frequency of the filter is programmable to be 1.25MHz, 2.5MHz, 5MHz and 10MHz. For low-power systems powered by a single-cell battery, the SC filter was elaborately designed to operate at 1.2V power supply. Simulation result shows that the 3rd-order input intercept point (IIP3) can be up to 27dBm. The filter was fabricated in a $0.25-{\mu}m$ 1P5M standard CMOS technology and measured frequency responses show good agreement with the simulation ones. The current consumption is 34mA at a 1.2V power supply.

• Journal of Electrical Engineering and Technology
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• 제10권3호
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• pp.1015-1024
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• 2015

This paper introduces a low cost, high efficiency, high performance three-phase unified power quality conditioner (UPQC) by using four-switch three-phase inverters (FSTPIs) and an extra capacitor in the shunt active power filter (APF) side of the UPQC. In the proposed UPQC, both shunt and series APFs are developed by using FSTPIs so that the number of switching devices is reduced from twelve to eight devices. In addition, by inserting an additional capacitor in series with the shunt APF, the DC-link voltage in the proposed UPQC can also be greatly reduced. As a result, the system cost and power loss of the proposed UPQC is significantly minimized thanks to the use of a smaller number of power switches with a lower rating voltage without degrading the compensation performance of the UPQC. Design of passive components for the proposed UPQC to achieve a good performance is presented in detail. In addition, comparisons on power loss, overall system efficiency, compensation performance between the proposed UPQC and the traditional one are also determined in this paper. Simulation and experimental studies are performed to verify the validity of the proposed topology.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.528-532
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• 2004

Novel single-stage power factor correction AC/DC converter with low DC link voltage using new magnetic feedback technique is proposed in this paper. The Proposed converter has high power factor, tight output voltage regulation and low link capacitor voltage less than 450V for all the load range through the universal input line. This converter has also no dead-zone in the input current, which is seen in the conventional converter using the previous magnetic feedback technique. In this paper, the analysis of operations and features of the proposed converter is provided, and the experimental results of 90W-prototype shows the low harmonic distortions satisfied with EN 61000-3-2 Class D, high power factor and low link voltage less than 450V.

• 한국정보통신학회논문지
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• 제5권4호
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• pp.746-755
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• 2001

본 논문은 플라잉 커패시터 3-레벨 인버터 및 컨버터를 위한 스너버 회로를 제안하였다. 제안한 스너버회로는 Undeland 스너버를 기본 스너버로 사용하여 구성한 것으로서, 2-레벨 인버터에서 사용되어온 Undeland 스너버의 장점을 그대로 지니고 있다. 3-레벨 인버터 및 컨버터를 위해 제안한 스너버 회로와 기존의 RCD/RLD 스너버를 비교하면 1)사용소자의 수가 감소하며, 2) 낮은 과전압에 의한 스위칭 소자의 전압 스트레스가 감소하며, 3) 스너버 회로에서의 전력손실이 감소하여 전체 시스템에서의 효율이 개선된다. 본 논문에서는 제안한 스너버를 3-레벨 플라잉 커패시터 인버터에 적용하여 스너버 특성을 컴퓨터 시뮬레이션으로 분석하였으며 실험을 통해 제안한 스너버의 효용성을 입증하였다. 제안한 플라잉 커패시터 3-레벨 인버터 및 컨버터를 위한 스너버 회로를 구성하는 방법은 멀티레벨 인버터 및 컨버터에도 그대로 적용 할 수 있다.

• 마이크로전자및패키징학회지
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• 제29권1호
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• pp.1-6
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• 2022

The mobile device industry demands much higher levels of integration and lower costs coupled with a growing awareness of the complete system's configuration. A subsystem module package is similar to a board-level circuit that integrates a system function in a package beyond a System-in-Package (SiP) design. It is an advanced IC packaging solution to enhance the PDN and achieve a smaller form factor. Unlike a system-level design with a decoupling capacitor, a subsystem module package system needs to redefine the role of the capacitor and its configuration for PDN performance. Specifically, the design of package's form factor should include careful consideration of optimal PDN performance and the number of components, which need to define the decoupling capacitor's value and the placement strategy for a low impedance profile with associated cost benefits. This paper will focus on both the static case that addresses the voltage (IR) drop and AC analysis in the frequency domain with three specific topics. First, it will highlight the role of simulation in the subsystem module design for the PDN. Second, it will compare the performance of double-sided component placement (DSCP) motherboards with the subsystem module package and then prove the advantage of the subsystem module package. Finally, it will introduce three-terminal decoupling capacitor (decap) configurations of capacitor size, count and value for the subsystem module package to determine the optimum performance and package density based on the cost-effective model.

• Journal of Power Electronics
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• 제19권3호
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• pp.645-654
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• 2019

In this paper, a new high step up DC/DC converter with a modified super-lift technique is presented. The coupled inductor technique is combined with the super-lift technique to provide a tenfold or more voltage gain with a proper duty cycle and a low turn ratio. Due to a high conversion ratio, the voltage stress on the semiconductor devices is reduced. As a result, low voltage ultra-fast recovery diodes and low on resistance MOSFET can be used, which improves the reverse recovery problems and conduction losses. This converter employs a passive clamp circuit to recycle the energy stored in the leakage inductance. The proposed convertor features a high conversion ratio with a low turn ratio, low voltage stress, low reverse recovery losses, omission of the inrush currents of the switch capacitor loops, high efficiency, small volume and reduced cost. This converter is suitable for renewable energy applications. The operational principle and a steady-state analysis of the proposed converter are presented in details. A 200W, 30V input, 380V output laboratory prototype circuit is implemented to confirm the theoretical analysis.

• 전기학회논문지P
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• 제59권3호
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• pp.325-329
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• 2010

Capacitor has been used principally for the power factor compensation long ago. However now it does as passive filter to reduce harmonics of nonlinear load with reactor. Most of the customer's low-voltage feeder has been designed with approximately balanced and connected at the 3 phase four wire system. But voltage and current unbalance is appeared by the mixing operation of single or three phase load etc. The addition of reactor at the condenser may rise its terminal voltage. Voltage and current values above rating can act on electrical stress on the condenser. In this paper, we calculated and measured that voltage, current and capacity of condenser are changed under the voltage balance. We conclude that magnitude and deviation of phase voltage act on major point of electrical stress.