• 제목/요약/키워드: Low Output Voltage

검색결과 1,334건 처리시간 0.03초

Novel Carrier-Based PWM Strategy of a Three-Level NPC Voltage Source Converter without Low-Frequency Voltage Oscillation in the Neutral Point

  • Li, Ning;Wang, Yue;Lei, Wanjun;Niu, Ruigen;Wang, Zhao'an
    • Journal of Power Electronics
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    • 제14권3호
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    • pp.531-540
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    • 2014
  • A novel carrier-based PWM (CBPWM) strategy of a three-level NPC converter is proposed in this paper. The novel strategy can eliminate the low-frequency neutral point (NP) voltage oscillation under the entire modulation index and full power factor. The basic principle of the novel strategy is introduced. The internal modulation wave relationship between the novel CBPWM strategy and traditional SPWM strategy is also studied. All 64 modulation wave solutions of the CBPWM strategy are derived. Furthermore, the proposed CBPWM strategy is compared with traditional SPWM strategy regarding the output phase voltage THD characteristics, DC voltage utilization ratio, and device switching losses. Comparison results show that the proposed strategy does not cause NP voltage oscillation. As a result, no low-frequency harmonics occur on output line-to-line voltage and phase current. The novel strategy also has higher DC voltage utilization ratio (15.47% higher than that of SPWM strategy), whereas it causes larger device switching losses (4/3 times of SPWM strategy). The effectiveness of the proposed modulation strategy is verified by simulation and experiment results.

효율적 버퍼 주파수 보상을 통한 LDO 선형 레귤레이터 (LDO Linear Regulator Using Efficient Buffer Frequency Compensation)

  • 최정수;장기창;최중호
    • 대한전자공학회논문지SD
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    • 제48권11호
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    • pp.34-40
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    • 2011
  • 본 논문은 낮은 출력 저항을 버퍼를 사용하여 주파수 보상을 수행한 LDO 선형 레귤레이터에 관한 것이다. 주파수 보상을 위해 제안하는 버퍼는 두 개의 shunt 피드백 루프를 사용하여 출력 저항을 최소화함으로써 이를 통해 LDO 선형 레귤레이터 전체의 부하 및 입력 전압에 따른 레귤레이션 성능을 개선할 수 있고 저전압에서도 낮은 출력 저항을 유지함으로 휴대기기 응용에 있어서도 적합하다. 또한 외부 디지털 제어를 통한 LDO 선형 레귤레이터의 출력 전압을 가변함으로써 외부 MCU와의 인터페이스를 개선하기 위한 기준 전압 제어 기법을 나타내었다. 구현된 LDO 선형 레귤레이터는 2.5V~4.5V의 입력 전압에 대하여 동작하며 최대 300mA의 부하 전류를 0.6~3.3V의 출력 전압에 대하여 제공할 수 있다.

광전지 패널과 DC-DC 컨버터 출력의 직렬 접속을 이용한 고효율 PV 시스템 (A high efficient PV system using series connection of DC-DC converter's output with photovoltaic panel)

  • 김호성;김종현;민병덕;유동욱;홍지태;이동길;김희제
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2008년도 제39회 하계학술대회
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    • pp.1146-1147
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    • 2008
  • PV Power Conditioning System (PCS) must have high conversion and low cost. Generally, PV PCS uses either a single converter or multilevel module integrated converter (MIC). Each of these approaches has both advantage and disadvantage. For a high conversion efficiency and low cost of PV module, this paper proposes series connection of module integrated DC-DC converter's output with PV panel. Output voltage of PV panel is connected to the output capacitor of flyback converter. Thus, converter's output voltage is added to the output voltage of PV panel. Isolated DC-DC converter generates only the difference voltage between the PV panel voltage and the required total output voltage. This method reduces power level of DC-DC converter and enhances the energy conversion efficiency compared with conventional DC-DC converter.

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강압형과 하프 브리지 직렬형 DC-DC 컨버터 (Buck and Half Bridge Series DC-DC Converter)

  • 김창선
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
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    • 제54권12호
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    • pp.616-621
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    • 2005
  • We considered of the buck and half bridge series DC-DC converter. It has good applications in areas with low voltage/high current, wide input voltage. The buck converter ratings and the half bridge converter ratings are $36\~72V$ input and 22V/5A output, $19\~24V$ input and 3.3V/30A output, respectively. Developed the buck and half Bridge series DC-DC converter ratings are of $36\~72V$ input and 3.3V/30A output. The buck converter is operated with zero voltage switching process to reduce the switching losses. The $80.1\%\~97.6\%$ of the efficiency is measured at $18.4{\mu}H$ output filter inductance of buck converter. In the half bridge converter, the $86\%\~96.4\%$ efficiency is measured at 150kHz switching frequency with PQI core. In the case of synchronized the buck and half bridge DC-DC converter, the measured efficiency is higher than that of the unsynchronized converter. In the synchronized converter, the maximum efficiency is measured up to $92.3\%$ with PQI core at 150kHz. 7A output.

A Single-Stage AC/DC Converter with Low Voltage Stresses and Reduced Switching Losses

  • Kim, Kyu-Tae;Choi, Woo-Young;Kwon, Jung-Min;Kwon, Bong-Hwan
    • Journal of Power Electronics
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    • 제9권6호
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    • pp.823-834
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    • 2009
  • This paper proposes a high-efficiency single-stage ac/dc converter. The proposed converter features low voltage stresses and reduced switching losses. It operates at the boundary of discontinuous- and continuous-conduction modes by employing variable switching frequency control. The turn-on switching loss of the switch can be reduced by turning it on when the voltage across it is at a minimum. The voltage across the bulk capacitor is independent of the output loads and maintained within the practical range for the universal line input, so the problem of high voltage stress across the bulk capacitor is alleviated. Moreover, the voltage stress of the output diodes is clamped to the output voltage, and the output diodes are turned off at zero-current. Thus, the reverse-recovery related losses of the output diodes are eliminated. The operational principles and circuit analysis are presented. A prototype circuit was built and tested for a 150 W (50V/3A) output power. The experimental results verify the performance of the proposed converter.

Interleaved High Step-Up Boost Converter

  • Ma, Penghui;Liang, Wenjuan;Chen, Hao;Zhang, Yubo;Hu, Xuefeng
    • Journal of Power Electronics
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    • 제19권3호
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    • pp.665-675
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    • 2019
  • Renewable energy based on photovoltaic systems is beginning to play an important role to supply power to remote areas all over the world. Owing to the lower output voltage of photovoltaic arrays, high gain DC-DC converters with a high efficiency are required in practice. This paper presents a novel interleaved DC-DC boost converter with a high voltage gain, where the input terminal is interlaced in parallel and the output terminal is staggered in series (IPOSB). The IPOSB configuration can reduce input current ripples because two inductors are interlaced in parallel. The double output capacitors are charged in staggered parallel and discharged in series for the load. Therefore, IPOSB can attain a high step-up conversion and a lower output voltage ripple. In addtion, the output voltage can be automatically divided by two capacitors, without the need for extra sharing control methods. At the same time, the voltage stress of the power devices is lowered. The inrush current problem of capacitors is restrained by the inductor when compared with high gain converters with a switching-capacitor structure. The working principle and steady-state characteristics of the converter are analyzed in detail. The correctness of the theoretical analysis is verified by experimental results.

16 V 급 NMOSFET 소자의 낮은 게이트 전압 영역에서 출력저항 개선에 대한 연구 (Design and Analysis of 16 V N-TYPE MOSFET Transistor for the Output Resistance Improvement at Low Gate Bias)

  • 김영목;이한신;성만영
    • 한국전기전자재료학회논문지
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    • 제21권2호
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    • pp.104-110
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    • 2008
  • In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

비대칭 전압 제어를 이용한 단상 임베디드 Z-소스 DC-AC 인버터 (A Single-Phase Embedded Z-Source DC-AC Inverter by Asymmetric Voltage Control)

  • 오승열;김세진;정영국;임영철
    • 전력전자학회논문지
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    • 제17권4호
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    • pp.306-314
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    • 2012
  • In case of the conventional DC-AC inverter using two DC-DC converters with unipolar output capacitor voltages, for generating the AC output voltage, the output capacitor voltages of its each DC-DC converter must be higher than the DC input voltage. To solve this problem, this paper proposes a single-phase DC-AC inverter using two embedded Z-source converters with bipolar output capacitor voltages. The proposed inverter is composed of two embedded Z-source converters with common DC source and output AC load. The AC output voltage is obtained by the difference of the output capacitor voltages of each converter. Though the output capacitor voltage of converter is relatively low compared to the conventional method, it can be obtained the same AC output voltage. Moreover, by controlling asymmetrically the output capacitor voltage, the AC output voltage of the proposed system is higher than the DC input voltage. To verify the validity of the proposed system, a DSP(TMS320F28335) based single-phase embedded Z-source DC-AC inverter was made and the PSIM simulation was performed under the condition of the DC source 38V. As controlled symmetrically and asymmetrically the output capacitor voltages of each converter, the proposed inverter could produce the AC output voltage with sinusoidal waveform. Particularly, in case of asymmetric control, a higher AC output voltage was obtained. Finally, the efficiency of the proposed system was measured as 95% and 97% respectively in case of symmetric and asymmetric control.

A Reduced-Swing Voltage-Mode Driver for Low-Power Multi-Gb/s Transmitters

  • Song, Hee-Soo;Kim, Su-Hwan;Jeong, Deog-Kyoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제9권2호
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    • pp.104-109
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    • 2009
  • At a lower supply voltage, voltage-mode drivers draw less current than current-mode drivers. In this paper, we newly propose a voltage-mode driver with an additional current path that reduces the output voltage swing without the need for complicated additional circuitry, compared to conventional voltage-mode drivers. The prototype driver is fabriccated in a 0.13-$^{\mu}m$ CMOS technology and used to transmit data streams at the rate of 2.5 Gb/s. Deemphasis is also implemented for the compensation of channel attenuation. With a 1.2-V supply, it dissipates 8.0 mA for a 400-mV output voltage swing.

단위 역률을 갖는 3상 강압형 다이오드 정류기에서 고조파 주입에 의한 DC 리플전압 저감 기법 (A DC Ripple Voltage Suppression Scheme by Harmonic Injection in Three Phase Buck Diode Rectifiers with Unity Power Factor)

  • 고종진
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2000년도 전력전자학술대회 논문집
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    • pp.305-308
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    • 2000
  • A technique to suppress the low frequency ripple voltage of the DC output in three phase buck diode rectifiers is presented in this paper. The proposed pulse frequency modulation methods and duty ratio modulation methods are employed to regulate the output voltage of the buck diode rectifiers and guarantee zero-current -switching(ZCS) of the switch over the wide load range The proposed control methods used in this paper provide generally good performance such as low THD of the input line current and unity power factor. IN addition control methods can be effectively used to suppress the low frequency ripple voltage appeared in the dc output voltage. The harmonic injection technique illustrates its validity and effectiveness through the simulations.

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