• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.198-202
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• 1987

The regulator problem can be considered as some impulsive disturbance rejection one. In this point of view, the rate of decay is one of important factors for regulation and depends on how negative the real parts of the eigenvalues of closed-loop system. The algorithm that the closed-loop system has eigenvalues lying within a vertical. strip is useful for rapid disturbance rejection. This paper presents a design method for a linear quadratic regulator of two-time scale system with eigenvalues in a vertical strip by use of time-scale separation property.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.61.2-61
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• 2001

The purpose of the initial alignment of a SDINS is to get a coordinate transformation matrix from the body frame to the navigation frame. The initial alignment is one of the most important processes in the navigation system since its error has a large influence on the navigation solution. In this paper, a real-time initial alignment algorithm for the SDINS is developed using the Kalman filter. The steady state error analysis is performed for the developed Kalman filter technique and the gyrocompass loop method. The performance of the developed alignment method is compared with the gyrocompass loop method through the real-time alignment experiments.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.209-212
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• 2000

In this paper, effect of imperfect power control on performance of a pseudonoise (PN) code tracking loop is analyzed and simulated for a direct-sequence/code-division multiple access (DS/CDMA) system. The multipath fading channel is modeled as a two-ray Rayleigh fading model. Power control error is modeled as a log-normally distributed random variable. The tracking performance of DLL (delay-locked-loop) is evaluated in terms of tracking jitter and mean-time-to-lose-lock (MTLL). From the simulation results, it is shown that the PN tracking performance is very sensitive to the power control error.

• Journal of Convergence for Information Technology
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• v.9 no.8
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• pp.45-52
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• 2019

This paper proposes the design of a closed-loop stepping motor drive for real-time Ethernet (RTE), which can be easily applied to a variety of RTE protocols. The proposed design is divided into a closed-loop step motor drive which can be reused for various types of RTE protocol and RTE module developed for each specific RTE protocol. It is based on a layered architecture so that the motion control algorithm can be easily reused independently of the RTE protocol and motion profile. To verify the proposed design, closed-loop motor drives based on EtherCAT and Mechatrolink III were developed and their performances were evaluated. Cycle time was measured to verify the real-time communication performance of the developed EtherCAT and Mechatrolink III based motor drive. As a result, the EtherCAT was 7.5 times faster than the Mechatrolink III when 32 motor drives were connected.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.21-30
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• 1994

We discussed the Distributed Control System's design on preface and analyzed time of the real-time communication by using designed system. The DCS proposed in this thesis was implemented to network file system having recovery advantage and shared memory method to access file system of a Remote Station with ease. Also, this system minimized the network delay-time by using the real-time VME147 board. In implemented DCS, the performance analysis of real-time process of a Remote Station was done to get the total time for reak-tune communication from a Remote Station to the Central Station after terminating of process. For the analysis of system performance, we experiented by three steps. Firstly, we measuredthe processing the of LOOP function that real-time CPU convertes to-2,500~10.000 values from the input data of the Analog Interface Card. Secondly, we measured the processing time of the LOGIC function and the LOOP function. Lastly, we measured total processing time for communication from a Remote Station to the Centrol Station.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.401-404
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• 2015

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.12
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• pp.13-19
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• 2008

In this paper, we propose a new CL-OSTBC (Closed Loop Orthogonal Space-Time Block Code) scheme for four transmit antennas and compare the scheme with existing closed loop schemes on the performance of BER (Bit Error Rate). In the proposed scheme, a transmitter receives channel feedback information and combines modulated symbols by the symbol combiner, and transmits the symbols encoded by the space-time block encoder. As a result, the proposed scheme achieves full-rate and maximal channel gains by more efficient utilization of the channel feedback information. Moreover, the scheme can reduce computation complexity by using a linear detector. Simulation results on the BER performance show that the proposed CL-OSTBC scheme outperforms existing CL-OSTBC schemes.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.184-188
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• 2001

In this paper, a new fully digital control method for single-phase UPS inverter, which is based on the double control loop such as the outer voltage control loop and inner current control loop, is proposed. The inner current control loop is designed and implemented in the form of internal model control and takes the presence of computational time-delay into account. Therefore, this method provides an overshoot-free reference-to-output response. In the proposed scheme, the outer voltage control loop employing P controller with resonance model implemented by a DSP is introduced. The proposed resonance model has an infinite gain at resonant frequency, and it exhibits a function similar to an integrator for AC component. Thus the outer voltage control loop causes no steady state error as regard to both magnitude and phase. The effectiveness of the proposed control system has been demonstrated by the simulation and experimental results respectively.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.163-167
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• 2000

This paper presents the digital control of single-phase power factor correction(PFC) converter which has the variable gain according to the condition of inner control loop error. Generally the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This has a bad influence on the power factor because current loop doesn't operate smoothly in the condition that input voltage is low In particular a digital controller has more time delay than an analog controller and degrades This drops the phase margin of the total digital PFC system,. It causes the problem that the gain of current control loop isn't increased enough. In addition the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult The digital PFC controller presented in this paper has a variable gain of current control loop according to input voltage. The 1kW converter was used to verify the efficiency of the digital PFC controller.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.333-336
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• 2000

Modem standard CMOS process technology suffer from so large amount of PVT i.e process, voltage and temperature variation over 30% of its desired value that accurate resistor value is hard to be achieved. A filter using switched-capacitor(SC) circuit has a time constant proportional to relative capacitor area ratio rather than its absolute value. If the PLL's loop filter were made out of SC circuit, there could be much less PVT variation problem. Furthermore, programmability on the loop filter can be achieved In this paper, we present the PLL with SC loop filter. The accuracy provided by SC filter would be helpful to enhance PLL's locking behaviour.