• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2A
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• pp.96-101
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• 2003

This paper is on the user equipment (UE) side time tracker design and implementation of the wideband code division multiple access (WCDMA) system. The time tracker is constructed as a second order closed loop including time error detector (TED), loop filter (LP), numerically controlled oscillator (NCO), and sample selector (SS). Through the simulation, we found the gain of the TED as a function of the CPICH power contribution to the total transmission power of the base station. Also we derived the transfer function of the loop and the BER versus DPCH power relationships where timing offsets and loop noise bandwidths are used as parameters. In the curve, we can conclude that there are appropriate loop noise bandwidths according to the given environments for the better performance.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.1201-1204
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• 1996

The previous results on LTR methods for time delay systems need the solution of the operator-type Riccati equation. In addition, it can be difficult to make the target loop shape representing the design specification. This paper proposes a new LTR method for input-delayed systems using well-established LTR method for non-delay systems. For doing this, a time delay margin is derived and the time delay of the input-delayed systems is assumed less than equal to the time delay margin. A simple example is presented for illustrations.

• Nuclear Engineering and Technology
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• v.30 no.6
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• pp.531-540
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• 1998

The DYLAM-3 code which overcomes the limitation of event tree/fault tree was applied to LOOP (Loss of Off-site Power) in the mid-loop operation employing HEPs (Human Error Probabilities) supplied by the ASEP (Accident Sequence Evaluation Program) and the SEPLOT (Systematic Evaluation Procedure for Low power/shutdown Operation Task) procedure in this study. Thus the time history of core uncovery frequency during the mid-loop operation was obtained. The sensitivity calculations in the operator's actions to prevent core uncovery under LOOP in the mid-loop operation were carried out. The analysis using the time dependent HEP was performed on the primary feed & bleed which has the most significant effect on core uncovery frequency. As the result, the increment of frequency is shown after 200 minutes duration of simulation conditions. This signifies the possibility of increment in risk after 200 minutes. The primary feed & bleed showed the greatest impact on core uncovery frequency and the recovery of the SCS (Shutdown Cooling System) showed the least impact. Therefore the efforts should be taken on the primary feed & bleed to reduce the core uncovery frequency in the mid-loop operation. And the capability of DYLAM-3 in applying to the time dependent concerns could be demonstrated.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.4
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• pp.148-155
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• 1996

A loop structure optimization algorithm is proposed for generting a set of efficient codes for loop structure in order to optimize RISC compiler codes. Since there are so many loop structure in the program, most of the execution time is used to process looping codes. Thus, reduction of loop instructions is more effective than optimizing codes outside the loop. The proposed algorithm presents a method to combine several different loops into a simple loop. Therefore, rather than executing each loop independently, loops in the program are serached, analyzed, and finally created some relative informtion such as dependency and range. In doing so, the loops in the program can efficiently be recombined and restructured. As a result, the overall execution time for the program of the sequential programming language is reduced.

• Nuclear Engineering and Technology
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• v.15 no.3
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• pp.188-196
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• 1983

A simplified fast-running system code is developed to simulate loop transients such as pump coastdown, loop failures and natural circulation. Special emphasis is put on the numerical investigation of the natural circulation system with multiloop. For this purpose, 5 governing equations are derived, and they are discretized by the space-time integration technique. The developed computer program is applied to three sample problems; transition from 2-loop to 1-loop operation, transition from 1-loop to 2-loop operation, and the transient behavior with decay power in the case of 2-loop operation.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.786-790
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• 1987

An optimization problem minimizing n given time-weighted performance index for discrete-time linear multi-input systems is investigated for the prespecified closed-loop eigenvalues. Necessary conditions for an optimality of the controller that satisfies the specified closed-loop eigenvalues are derived. A computational algorithm solving the optimal constant feedback gain is presented and a numerical example is given to show the effect of a time-weighted performance index on the transient responses.

• Journal of Power Electronics
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• v.11 no.2
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• pp.156-162
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• 2011

The control loop time delay caused by sampling, the zero-order-holder effect and calculations is inevitable in the digital control of dc-dc switching converters. The time delay will limit the bandwidth of the control loop and therefore degrade the transient performance of digital systems. In this paper, the quantization time delay effects with different time delay values based on a generic second-order system are analyzed. The conclusion that the bandwidth of digital control is reduced by about 20% with a one cycle delay and by 50% with two cycles of delay in comparison with no time delay is obtained. To compensate the time delay and to increase the control loop bandwidth, a duty ratio predictive control scheme based on linear extrapolation is proposed. The compensation effect and a comparison of the load variation transient response characteristics with analogy control, conventional digital control and duty ratio predictive control with different time delay values are performed on a point-of-load Buck converter by simulations and experiments. It is shown that, using the proposed technique, the control loop bandwidth can be increased by 50% for a one cycle delay and 48.2% for two cycles of delay when compared to conventional digital control. Simulations and experimental results prove the validity of the conclusion of the quantization effects of the time delay and the proposed control scheme.

• Journal of information and communication convergence engineering
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• v.3 no.1
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• pp.18-22
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• 2005

This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. When the phase error is large, the PLL increases the loop bandwidth and reduces locking time. When the phase error is small, the PLL decreases the loop bandwidth and minimizes output jitters. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. A 1.28-GHz CMOS phase-locked loop with adaptive bandwidth control is designed with 0.35 $mu$m CMOS technology. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO are approximately -80dBc.

• Journal of Power Electronics
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• v.11 no.2
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• pp.113-119
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• 2011

This paper presents a DSP based direct digital control design and implementation for a high power boost converter. A single loop and dual loop voltage control are digitally implemented and compared. The real time workshop (RTW) is used for automatic real-time code generation. Experimental results of a 20 kW boost converter based on the TMS320F2808 DSP during reference voltage changes, input voltage changes, and load disturbances are presented. The results show that the dual loop control achieves better steady state and transient performance than the single loop control. In addition, the experimental results validate the effectiveness of using the RTW for automatic code generation to speed up the system implementation.

• Nuclear Engineering and Technology
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• v.53 no.2
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• pp.688-694
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• 2021

The aim of this work is the analysis, design and hardware implementation of the fractional-order point kinetics (FNPK) model along with its closed-loop controller. The stability and closed-loop control of FNPK models are critical issues. The closed-loop stability of the controller-plant structure is established. Further, the designed PI/PD controllers are implemented in real-time on a DSP processor. The simulation and real-time hardware studies confirm that the designed PI/PD controllers result in a damped stable closed-loop response.