• Journal of Power Electronics
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• v.19 no.4
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• pp.1000-1010
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• 2019

The use of internal-model-based linear controller, such as resonant controller, is a well-established technique for the current control of grid-connected systems. Attractive properties for resonant controllers include their two-sequence tracking ability, the simple control structure, and the reduced computational burden. However, in the case of continuous-designed resonant controller, the transient performance is inevitably degraded at a low switching frequency. Moreover, available design methods for resonant controller is not able to realize the direct design of transient performances, and the anticipated transient performance is mainly achieved through trial and error. To address these problems, the zero-order-hold (ZOH) characteristic and inherent time delay in digital control systems are considered comprehensively in the design, and a corresponding hold-equivalent discrete model of the grid-connected converter is then established. The relationship between the placement of closed-loop poles and the corresponding transient performance is comprehensively investigated to realize the direct mapping relationship between the control gain and the transient response time. For the benefit of automatic tuning and real-time adaption, analytical expressions for controller gains are derived in detail using the required transient response time and system parameters. Simulation and experimental results demonstrate the validity of the proposed method.

• Journal of the Korea Institute of Military Science and Technology
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• v.24 no.6
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• pp.577-590
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• 2021

In this paper, we theoretically analyzed the self-alignment/navigation performance in the accelerometer resonance state generated by dither motion of ring laser gyroscope in LINS and verified it through simulation. As a result of analysis, it is confirmed that the amplitude of the accelerometer measurement amplified in the accelerometer resonance state is decreased in the process of sampling per the navigation calculation period and that frequency is changed by the aliasing effect too. It was also analysed that the attitude error in self-alignment is determined by the amplitude/frequency of the accelerometer measurement, the gain of the self-alignment loop, and the velocity and position error in the navigation is determined by the amplitude/frequency/phase error of the accelerometer measurement. This analysis and simulation results show that the self-alignment and navigation performance is not be degraded only when the amplification factor of the accelerometer measurement in the accelerometer resonance state is 3 or less

• Journal of IKEEE
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• v.27 no.3
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• pp.258-264
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• 2023

This paper proposes an LDO regulator with a built-in ESD (Electro Static Discharge) protection circuit to effectively operate and prevent destruction of the LDO (Low Drop Out) regulator according to the load current. The proposed LDO regulator can more effectively adjust the gate node voltage of the pass transistor according to the output voltage of the LDO regulator by using an additional feedback current circuit structure. In addition, it is expected to have high reliability for the ESD situation by embedding a new structure that increases the holding voltage by about 2V by reducing the current gain on the SCR loop by adding a P+ bridge to the existing ESD protection device.

• Journal of IKEEE
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• v.28 no.1
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• pp.20-25
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• 2024

This paper presents a new dualband shared-aperture microstrip antenna to operate in the S-Band of 2 GHz and X-Band of 8 GHz, for a Low Earth Orbit satellite antenna system. The proposed antenna incorporates two types of patches those are a rectangular loop-shaped for the S-Band and a square patch for the X-Band. Each patch are optimized for its respective operating band with minimal interference. The proposed antenna achieves a bandwidth of 16 MHz in the S-Band and 572 MHz in the X-Band. The highest gain is measured 7.14 dBi at 1.99 GHz and 7.95 dBi at 7.88 GHz. The proposed antenna exhibits half power beamwidths of 85 degree and 80 degree at 1.99 GHz and 7.88 GHz, respectively. The proposed dualband shared-aperture microstrip antenna may be a good candidate for as a feeding system of a dualband reflectarray antenna With its unidirectional radiation pattern from excellent agreement between simulation and measurement results.

• Journal of the Korea institute for structural maintenance and inspection
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• v.12 no.5
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• pp.65-73
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• 2008

Retaining large stability margin is essential in designing a feedback control system to deal with the uncertainties inherently existing in the mathematical model and the control apparatus. The LQG controller in general loses the stability margin due to the embed Kalman filter. The performance of a control system called LTR with a DUOX structure(LTR/DOUX) to overcome the demerit of LQG controller is to be investigated from the responses in both the time and the frequency domain. The results indicated that the LTR/DOUX recovered the gain margin of 30dB approximately 20 times more than that of LQG/DOUX, resulting in a robust stable control system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.34-41
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• 2011

This paper presents a wide tuning range, fine-resolution DCO (Digitally Controlled Oscillator) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. To cover the wide tuning range, an automatic three-step coarse tuning scheme is proposed. The DCO total frequency tuning range is 1.4 GHz (2.1 GHz to 3.5 GHz), it is 58 % at 2.4 GHz. An effective frequency resolution is 0.14 kHz/LSB. The proposed DCO is implemented in 0.13 ${\mu}m$ CMOS process. The total power consumption is 6.6 mW from a 1.2 V supply voltage. The phase noise of the DCO output at 2.4 GHz is -120.67 dBc/Hz at 1 MHz offset.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12A
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• pp.2000-2011
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• 2001

In this Paper, we convert conventional low speed(1x, 6x) DVD systems designed by analog PLL(Phase Locked Loop) into digital PLL to operate at high speed systems flexibly, and present optimal DPLL model in high speed(20x) DVD systems. Especially, we focused on the design of DPLL that can overcome channel effects such as bulk delay, sampling clock frequency offset and asymmetry phenomenon in high speed DVD systems. First, the modified Early-Late timing error detector as digital timing recovery scheme is proposed. And the four-sampled compensation algorithm using zero crossing point as asymmetry compensator is designed to achieve high speed operation and strong reliability. We show that the proposed timing recovery algorithm provides enhanced performances in jitter valiance and SNR margin by 4 times and 3dB respectively. Also, the new four-sampled zero crossing asymmetry compensation algorithm provides 34% improvement of jitter performance, 50% reduction of compensation time and 2.0dB gain of SNR compared with other algorithms. Finally, the proposed systems combined with asymmetry compensator and DPLL are shown to provide improved performance of about 0.4dB, 2dB over the existing schemes by BER evaluation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.126-142
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• 2016

This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal $S_{22}$ and $S_{11}$ matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in $0.13{\mu}m$, 1-poly, 6-metal CMOS technology. The die area of the transceiver is $4mm{\times}3mm$. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.

• Nuclear Engineering and Technology
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• v.28 no.2
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• pp.137-149
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• 1996

The present study is to analyze an integral test, BETHSY test 6.9c, which represent loss of RURS accident under mid-loop operation. Both the pressurizer manway and the steam generator outlet plenum manway are opened as vent paths in order to prevent the system from pressurization by removing the steam generated in the core. The main purposes are to gain insights into the physical phenomena and identify sensitive parameters. Assessment of capability of CATHARE2 prediction can be established the effective recovery procedures using the code in an actual plant. Most of important physical phenomena in the experiment could be predicted by the CATHARE2 code. The peak pressure in the upper plenum is predicted higher than experimental value by 7 kPa since the differential pressure between the pressurizer and the surge line is overestimated. The timing of core uncovery is delayed by 500 seconds mainly due to discrepancy in the core void distribution. It is demonstrated that openings of the pressurizer manwey and the steam generator manway can prevent the core uncovery using only gravity feed injection. Although some disagreements are found in the detailed phenomena, the code prediction is considered reasonable for the overall system behaviors.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.39-47
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• 1998

A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.