• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.39 no.1
• /
• pp.16-21
• /
• 2002

In this paper, a dual type PFD(Phase Frequency Detector) for high speed PLL to improve output characteristics using TSPC(True Single Phase Clocking) circuit is proposed. The conventional 3-state PFD has problems with large dead-zone and long delay time. Therefore, it is not applicable to high-speed PLL(Phase-Locked Loop). A dynamic PFD with dynamic CMOS logic circuit is proposed to improve these problems. But, it has the disadvantage of jitter noise due to the variation of the duty cycle. In order to solve the problems of previous PFD, the proposed PFD improves not only the dead zone and duty cycle but also jitter noise and response characteristics by the TSPC circuit and dual structured PFD circuit. The PFD is consists of a P-PFD(Positive edge triggered PFD) and a N-PFD(Negative edge triggered PFD) and improves response characteristics to increase PFD gain. The Hspice simulation is performed to evaluate the performance of proposed PFD. From the experimental results, it has the better dead zone, duty cycle and response characteristics than conventional PFDs.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.16 no.1
• /
• pp.666-670
• /
• 2015

This paper presents radiation pattern reconfigurable antenna for Fitbit Flex wristband which detects vital signal. Also, the paper presents Specific Absorption Rate (SAR) from the loop-dipole radiation pattern reconfigurable antenna based on the position of human body. The proposed loop-dipole radiation pattern reconfigurable antenna produces two opposite side direction radiation pattern using two RF switches. The resonant frequency of the radiation pattern reconfigurable antenna is Bluetooth communication bandwidth (2.4 - 2.485 GHz) and the maximum gain of the proposed antenna is 1.96 dBi. The proposed antenna satisfied the standard SAR value of 1.6 W/kg in 1 g tissue of the human body when the Bluetooth communication input average power of 0.04 W is excited to five parts of human body (head, chest, stomach, back, wrist). The maximum SAR value of in this simulation is presented in the part of head.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.7C
• /
• pp.735-742
• /
• 2006

In this paper, we explain the operation scheme and fixed-point design method of DFE (Digital Front End), which performs DC offset compensation, automatic frequency control, and automatic gain control over the input signal to the UE (User Equipment) receiver of IEEE 802.16e OFDMA-TDD system. Then, we analyze the performance of DFE under ITU-R M. 1225 Veh-A 60km/h channel environment. To optimize the fixed-point design of DFE, we reduce the number of bit resulted from calculation without performance degradation, leading to the decreased complexity of the operation in H/W, and design the Loop filter with considering trade-off between the Acquisition time and the Stability.

• Journal of Sensor Science and Technology
• /
• v.6 no.2
• /
• pp.95-105
• /
• 1997

A new open-loop signal processing technique of digital phase tracking is known to have a Potential to solve the problems in the open-loop processor such as limited dynamic range, dependence on the optical intensity fluctuations, and dependence on gain fluctuations of signal path. But new problems with digital phase tracking must be solved before it can be a useful signal processing method. In this paper, barriers to the success of the digital phase tracking such as harmonics content, phase difference, amplitude variations of the phase modulation(PM) signal, bandwidth limit of the signal path, and the implementation of the mixer, are pointed out and their effects on the performance of the signal processor are analyzed to calculate the requirements of the signal processor for $1{\mu}rad$-grade FOG.

• Progress in Superconductivity
• /
• v.7 no.1
• /
• pp.46-51
• /
• 2005

We have developed control electronics to operate flux-locked loop (FLL), and analog signal filters to process FLL outputs for 64-channel Double Relaxation Oscillation SQUID (DROS) magnetocardiography (MCG) system. Control electronics consisting of a preamplifier, an integrator, and a feedback, is compact and low-cost due to larger swing voltage and flux-to-voltage transfer coefficients of DROS than those of dc SQUIDs. Analog signal filter (ASF) serially chained with a high-pass filter having a cut-off frequency of 0.1 Hz, an amplifier having a gain of 100, a low-pass filter of 100 Hz, and a notch filter of 60 Hz makes FLL output suitable for MCG. The noise of a preamplifier in FLL control electronics is $7\;nV/{\surd}\;Hz$ at 1 Hz, $1.5\;nV/{\surd}\;Hz$ at 100 Hz that contributes $6\;fT/{\surd}\;Hz$ at 1 Hz, $1.3\;fT/{\surd}\;Hz$ at 100 Hz in readout electronics, and the noise of ASF electronics is $150\;{\mu}V/{\surd}\;Hz$ equivalent to $0.13\;fT/{\surd}\;Hz$ within the range of $1{\sim}100\;Hz$. When DROSs are connected to readout electronics inside a magnetically shielded room, the noise of 64-channel DROS system is $10\;fT/{\surd}\;Hz$ at 1 Hz, $5\;fT/{\surd}\;Hz$ at 100 Hz on the average, low enough to measure human MCG.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.23 no.10
• /
• pp.1151-1156
• /
• 2012

In this paper, the baseband filter is proposed in order to maintain a constant sensitivity regardless of distances for 77 GHz automotive radar system. Using existing DCOC loop circuit can remove DC offset and also cancel differences of received power depending on the distance. Measured results show that the maximum gain is 51 dB and high pass cutoff frequency can be tuned from 5 kHz to 15 kHz. The slope of high pass filter can be tuned from -10 to -40 dB/decade for the distance compensation. The measured NF and IIP3 are 26 dB and +4.5 dBm with 4.3 mA at 1.0 V supply voltage, respectively. The fabricated die size $500{\mu}m{\times}1,050{\mu}m$ excluding the in/out pads.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.11 no.1
• /
• pp.84-92
• /
• 2000

A GaAs MESFET MMIC transmitter for 2.4 GHz wireless local loop handset is designed and fabricated. The transmitter consists of a double balanced active mixer and a two stage driver amplifier with voltage negative feedback. In particular, a pair of CS-CG(common source-common gate) structure compensates the reduction in dynamic range caused by unbalanced complementary IF input signals. And to suppress the leakage local power at RF port, the mixer is designed by using phase characteristic between the ports of MESFET. At the bias condition of 2.7 V and 55.2 mA, the fabricated MMIC transmitter with chip dimensions of $0.75\times1.75 mm^2$ obtains a measured conversion gain of 38.6 dB, output $P_{idB}$ of 11.6 dBm, and IMD3 at -5 dBm RF output power of -31.3 dBc. This transmitter is well suited for WLL handset.

• Journal of Digital Contents Society
• /
• v.19 no.1
• /
• pp.113-122
• /
• 2018

In level 3 automated vehicles, drivers are expected to encounter transition of control when the system reaches its limit. Drivers need to refocus their attention on the road ahead and gain situational awareness. Appropriate information should be conveyed during this period in order to prevent human errors. In this paper, we defined the takeover process as 'in-the-middle-of-the-loop' and conducted Task Analysis and Work Domain Analysis to find out information requirements. As a result, we specified required information types and interface considerations. Moreover, we conducted an experimental study to find how the information types affect drivers on situation awareness, cognitive load and reaction time. Consequently, we found different information on system transparency should be conveyed depending on the urgency of takeover situation and driver guidance could help drivers with better situation awareness after the takeover.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.12
• /
• pp.171-176
• /
• 2005

This study designed and fabricated a multi-purpose planar antenna for base stations that are accessible to DCS, WiBro, and ISM. The proposed antenna was designed into an open loop form from the existing monopole structure. The capacitance of the multi-purpose antenna was increased by the coupling of open parts. This makes the use of MMIC and LTCC convenient and the antenna is smaller and has a larger gain than existing antennas. The resonance distance and bandwidth can be adjusted by changing the open gap and the height of the loop of the antenna. The bandwidth of the designed antenna satisfies DCS, IMT-2000, WiBro, Bluetooth, wireless LAN and ISM bands based on VSWR 2. The entire frequency bandwidth is $58.75\%$ of $1.575GHz\~2.985GHz(1.41GHz)$. Also, the radiation pattern of the antenna displayed co-polarization and cross-polarization characteristics at 1.6GHz, 2.3GHz and 2.8GHz.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.5
• /
• pp.1886-1900
• /
• 2018

This paper proposes a confronting feedback control structure and controllers for positive output elementary super lift Luo converters (POESLLCs) working in discontinuous conduction mode (DCM). The POESLLC offers the merits like high voltage transfer gain, good efficiency, and minimized coil current and capacitor voltage ripples. The POESLLC working in DCM holds the value of not having right half pole zero (RHPZ) in their control to output transfer function unlike continuous conduction mode (CCM). Also the DCM bestows superlative dynamic response, eliminates the reverse recovery troubles of diode and retains the stability. The proposed control structure involves two controllers respectively to control the voltage (outer) loop and the current (inner) loop to confront the time-varying ON/OFF characteristics of variable structured systems (VSSs) like POESLLC. This study involves two different combination of feedback controllers viz. the proportional integral controller (PIC) plus sliding mode controller (SMC) and the fuzzy logic controller (FLC) plus SMC. The state space averaging modeling of POESLLC in DCM is reviewed first, then design of PIC, FLC and SMC are detailed. The performance of developed controller combinations is studied at different working states of the POESLLC system by MATLAB-Simulink implementation. Further the experimental corroboration is done through implementation of the developed controllers in PIC 16F877A processor. The prototype uses IRF250 MOSFET, IR2110 driver and UF5408 diodes. The results reassured the proficiency of designed FLC plus SMC combination over its counterpart PIC plus SMC.