• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2000년도 추계종합학술대회논문집
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• pp.165-168
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• 2000

In this paper, we propose a method, an optimized architecture of a device with an image signal process of a field unit to minimize the flick phenomenon that happens in direction of a color temperature at a color tone change. The proposed IIR loop filter has an optimized architecture and reduced hardware compared with previous filters. In order to achieve the optimization for the hardware complexity. It is designed by time-multiplexing architecture. The proposed IIR loop filter is synthesized by using the STD90 0.35um cell library.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.271-272
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• 2006

This paper presented a new experimental gain tuning technique for a Multi-Axis Servo System. First, the investigation for proportional gain of velocity control loop by using a Dynamic Signal Analyzer (DSA) was performed. Using the FUNCTION characteristic of DSA based on the Bode plot, the Bode plot of open loop transfer function was obtained. In turn, the integral gain of a servo controller can be found out by using the Integration time constant extracted from the Bode plot of open loop transfer function. In the meanwhile, the positional gain of the servo controller has been obtained by using the Bode plot of the closed loop transfer function. We have also proposed the technique to find out an optimal parameter of a notch filter, which has a great influence on vibration reduction, by using the damping factor extracted from the Bode plot of closed loop transfer function.

• Journal of Power Electronics
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• 제9권3호
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• pp.365-376
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• 2009

In this paper, the implementation of a three-phase shunt active power filter is presented. The filter is essentially three independent single-phase current-controlled voltage source inverters (CC-VSI) with a common DC bus. The CC- VSI is operated to directly control the AC grid current to be sinusoidal and in phase with the grid voltage without detecting the load currents. The APF consists of a current control loop, which shapes the grid currents to be sinusoidal and a voltage control loop, which regulates the active power balance of the system. The experimental results indicate that the active filter is able to handle predominantly the harmonics, as well as the unbalance and reactive power, so that the grid currents are sinusoidal, in phase with the grid voltages and symmetrical.

• ETRI Journal
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• 제30권4호
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• pp.615-617
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• 2008

A novel and compact elliptic-function bandpass filter is proposed in this letter. The techniques of slot etching and the addition of open stubs are applied to enhance the self-inductance and self-capacitance of hexagonal open-loop resonators. Thus, size reduction and improved transmission performance are obtained. Compared to the performance of the conventional design, the central frequency and insertion loss are reduced by 28% and 3.1 dB, respectively. Measurements show that the proposed filter has a fraction bandwidth of 23% at the central frequency of 1.84 GHz, and its insertion loss in the passband is less than -1.5 dB. The bandpass filter occupies only 12 mm${\times}$21.2 mm (approximately $0.24{\lambda}_g{\times}0.14{\lambda}_g$).

• 대한전자공학회논문지TC
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• 제42권10호
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• pp.1-8
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• 2005

본 논문에서는 ATSC 지상파 DTV 시스템에서 심볼 타이밍 동기 성능 개선을 위한 알고리즘을 제안한다. 일반적으로 심볼 타이밍 동기를 위해 사용되는 가드너 방법은 다중 경로 페이딩 환경에서 성능이 좋지만 지터에 의해 성능 열화가 발생한다. 지터량는 루프 필터 대역폭이 작을수록 작아지지만, 수렴속도는 느려지게 된다. 본 논문에서는 수렴속도는 빠르면서 수렴 후 지터량를 감소시키기 위해 일정시간마다 루프필터의 출력 값을 평균하고 이 평균값을 이용하여 옵셋량을 추정한 후 점차적으로 대역폭을 줄여 지터의 크기를 줄이는 알고리즘을 제안한다. 제안하는 알고리즘은 기존의 방식에 비해 수렴속도와 지터의 기에서 좋은 성능을 보인다.

• 한국전자파학회논문지
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• 제24권11호
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• pp.1074-1080
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• 2013

광대역에서 저 위상 잡음 특성을 갖는 주파수 합성기를 YTO를 이용하여 설계하였다. 위상 잡음을 낮추기 위해 분주비를 줄일 수 있는 offset PLL 구조를 사용하였다. 위상 잡음 모델링을 이용하여 PLL의 loop filter, YTO의 Main 드라이버 회로와 FM 드라이버 회로의 loop filter를 최적화하였다. 또한, 1 Hz 이하의 고해상도를 얻기 위하여 DDS를 기준 신호로 사용하였다. 제작된 주파수 합성기의 위상 잡음은 3.2~6.8 GHz에서 -107 dBc/Hz @10 kHz 이하로 측정되었다. 측정 결과와 위상 잡음 모델링을 통해 계산한 값과 비교한 결과, 잘 일치함을 확인함으로써 위상 잡음 모델링이 타당함을 검증하였다.

• Journal of Power Electronics
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• 제15권5호
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• pp.1286-1294
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• 2015

Capacitor current feedback active damping is extensively used in grid-connected converters with an LCL filter. However, systems tends to become unstable when the digital control delay is taken into account, especially in low switching frequencies. This paper discusses this issue by deriving a discrete model with a digital control delay and by presenting the stable region of an active damping loop from high to low switching frequencies. In order to overcome the disadvantage of capacitor current feedback active damping, this paper proposes a modified approach using grid current and converter current for feedback. This can expand the stable region and provide sufficient active damping whether in high or low switching frequencies. By applying the modified approach, the active damping loop can be simplified from fourth-order into second-order, and the design of the grid current loop can be simplified. The modified approach can work well when the grid impedance varies. Both the active damping performance and the dynamic performance of the current loop are verified by simulations and experimental results.

• Journal of Power Electronics
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• 제12권5호
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• pp.800-812
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• 2012

This paper analyses the mathematical model and control strategies of a Hybrid Active Power Filter with Injection Circuit (IHAPF). The control strategy based on the load harmonic current detection is selected. A novel control method for a IHAPF, which is based on the analyzed control mathematical model, is proposed. It consists of two closed-control loops. The upper closed-control loop consists of a single fuzzy logic controller and the IHAPF model, while the lower closed-control loop is composed of an Adaptive Network based Fuzzy Inference System (ANFIS) controller, a Neural Generalized Predictive (NGP) regulator and the IHAPF model. The purpose of the lower closed-control loop is to improve the performance of the upper closed-control loop. When compared to other control methods, the simulation and experimental results show that the proposed control method has the advantages of a shorter response time, good online control and very effective harmonics reduction.

• 한국군사과학기술학회지
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• 제19권3호
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• pp.379-386
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• 2016

In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.

• Journal of Power Electronics
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• 제15권4호
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• pp.1085-1092
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• 2015

In this paper, the expressions of the estimated information of a single-phase enhanced phase-locked loop (EPLL), when input signal contains harmonics and a DC offset while the fundamental component takes step changes, are derived. The theoretical analysis results indicate that in the estimated information, the n^th-order harmonics cause n+1^th-order periodic ripples, and the DC offset causes a periodic ripple at the fundamental frequency. Step changes of the amplitude, phase angle and frequency of the fundamental component cause a transient periodic ripple at twice the frequency. These periodic ripples deteriorate the performance of the EPLL. A hybrid filter based EPLL (HF-EPLL) is proposed to eliminate these periodic ripples. A delay signal cancellation filter is set at the input of the EPLL to cancel the DC offset and even-order harmonics. A sliding Goertzel transform-based filter is introduced into the amplitude estimation loop and frequency estimation loop to eliminate the periodic ripples caused by the residual input odd-order harmonics and step change of the input fundamental component. The parameter design rules of the two filters are discussed in detail. Experimental waveforms of both the conventional EPLL and the proposed HF-EPLL are given and compared with each other to verify the theoretical analysis and advantages of the proposed HF-EPLL.