• Journal of Broadcast Engineering
• /
• v.17 no.3
• /
• pp.503-518
• /
• 2012

In this paper, we propose a complexity-based parallelization method of the sample adaptive offset (SAO) algorithm which is one of HEVC in-loop filters. The SAO algorithm can be regarded as region-based process and the regions are obtained and represented with a quad-tree scheme. A offset to minimize a reconstruction error is sent for each partitioned region. The SAO of the HEVC can be parallelized in data-level. However, because the sizes and complexities of the SAO regions are not regular, workload imbalance occurs with multi-core platform. In this paper, we propose a LCU-based SAO algorithm and a complexity prediction algorithm for each LCU. With the proposed complexity-based LCU processing, we found that the proposed algorithm is faster than the sequential implementation by a factor of 2.38 times. In addition, the proposed algorithm is faster than regular parallel implementation SAO by 21%.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
• /
• 1991.04a
• /
• pp.95-98
• /
• 1991

회전 기기의 이상으로 인하여 발생하는 진동은 축 회전속도의 고주파 성분 (super-harmonic)이나 또는 분수조파 성분(sub-harmonic)으로 나타나는 경 우가 대부분이기 때문에 회전기기의 진동을 주파수 영역에서 해석함에 있어 파워 스펙트럼의 주파수 축을 Hz로 나타내기보다는 축 회전속도의 order로 써 나타내는 것이 매우 유용하다. 스펙트럼을 order로써 나타내기 위해서는 샘플링 시간을 축 회전속도와 동기(synchronization)시켜야 하는데 이 방법으 로는 회전축에 엔코더(encorder)를 부착하여 엔코더에서 발생하는 펄스 신호 를 이용하여 샘플링하는 방법과 order tracking 필터를 이용하는 방법이 있 다. 그러나 전자의 방법은 원하는 회전축마다 엔코더를 부착하여야 하며 경 우에 따라서는 엔코더를 부착하기가 어려운 경우도 있으며, 회전기기의 운전 개시나 종료시처럼 회전속도가 급격히 변화하는 경우에는 낮은 주파수에서 중첩(aliasig)에 의한 오차가 수반될 수도 있다. 후자의 방법은 order tracking 필터 이외에도 여러 부수장비가 필요하며 기준 주파수(즉 회전속 도)가 급격히 변화하는 경우 PLL(phase locked loop)에서 tracking 오차가 발생된다. 최근에 발표된 논문에서 일정한 시간간격으로 샘플링한 데이터들 로부터 신호를 재합성하여 회전축의 속도와 동기가 되도록 재 샘플링함으로 서 스펙트럼의 주파수를 회전속도의 order로써 나타내는 방법을 제시하였다. 그러나 위 논문에서는 신호의 재합성에 필요한 재합성 필터(reconstruction filter)의 설계 방법에 대하여 구체적인 언급이 없이 다만 결과만을 논하였다. 따라서 본 논문에서는 재합성 필터의 설계 방법에 대하여 구체적인 방법을 제시하고 또한 동기화 샘플링의 장점 및 고려 사항에 대하여 고찰하였다. 고려한 능동 소음제어 에 대해 연구하였다. 경량화 추세에 따라 지반이나 케이싱이 경량이거나 유연하여 회전축과 동적으로 연성된 경우 회전축-베어링-지반으로 이루어진 2중구조의 회전축 계 동특성을 해석할 수 있는 프로그램을 개발하므로서 회전 기계류의 진동 전반에 걸친 문제점에 대한 그 원인과 현상을 명확히 분석하여 국내의 전기 계류의 보다 신뢰성있는 설계 및 제작자료를 확보하는데 기여할 수 있게 하 였다.존의 small molecular Gd-chelate에 비해 매우 큼을 알 수 있었다. MnPC는 간세포에 흡수된 후 담도계로 배출되는 간특이성 조영제임을 확인하였다. 장비 내에서 반복 시행한 평균값의 차이는 대체적으로 유의한 차이가 없었으나, 다른 장비에서 반복 시행한 장비간의 사이에는 유의한 차이가 있는 경우가 더 많았다. 따라서 , MRS 검사를 소뇌나 뇌교의 어떤 절환에 적용하기 전에 각 장비 마다 정상 기준치를 반드시 얻은 후에 이상여부를 판 정하는 것이 필수적이라고 생각된다.EX> 이상이 적절한 진단기준으로 생각되었다. $0.4{\;}\textrm{cm}^3$ 이상의 좌우 부피차를 보이는 모든 증례에서 육안적으로도 해마위축이 뚜렷이 나타났다. 결론 : MR영상을 이용한 해마의 부피측정은 해마경화증 환자의 진단에 있어 육안적인 MR 진단이 어려운 제한된 경우에만 실제적 도움을 줄 수 있는 보조적인 방법으로 생각된다.ofile whereas relaxivity at high field is not affected by τS. On the other hand, the change in τV does not affect low field profile but strongly in fluences on both inflection fie이 and the maximum relaxivity value. The re

• The Journal of the Korea institute of electronic communication sciences
• /
• v.14 no.6
• /
• pp.1249-1256
• /
• 2019

In this paper, we propose a new algorithm to remove acoustic feedback and noise in hearing aids. Instead of using the conventional FIR structure, this algorithm is a deep learning algorithm using neural network adaptive prediction filter to improve the feedback and noise reduction performance. The feedback canceller first removes the feedback signal from the microphone signal and then removes the noise using the Wiener filter technique. Noise elimination is to estimate the speech from the speech signal containing noise using the linear prediction model according to the periodicity of the speech signal. In order to ensure stable convergence of two adaptive systems in a loop, coefficient updates of the feedback canceller and noise canceller are separated and converged using the residual error signal generated after the cancellation. In order to verify the performance of the feedback and noise canceller proposed in this study, a simulation program was written and simulated. Experimental results show that the proposed deep learning algorithm improves the signal to feedback ratio(: SFR) of about 10 dB in the feedback canceller and the signal to noise ratio enhancement(: SNRE) of about 3 dB in the noise canceller than the conventional FIR structure.

• Journal of Broadcast Engineering
• /
• v.23 no.3
• /
• pp.383-394
• /
• 2018

In this paper, we investigate image and video compression techniques based on deep learning which are actively studied recently. The deep learning based image compression technique inputs an image to be compressed in the deep neural network and extracts the latent vector recurrently or all at once and encodes it. In order to increase the image compression efficiency, the neural network is learned so that the encoded latent vector can be expressed with fewer bits while the quality of the reconstructed image is enhanced. These techniques can produce images of superior quality, especially at low bit rates compared to conventional image compression techniques. On the other hand, deep learning based video compression technology takes an approach to improve performance of the coding tools employed for existing video codecs rather than directly input and process the video to be compressed. The deep neural network technologies introduced in this paper replace the in-loop filter of the latest video codec or are used as an additional post-processing filter to improve the compression efficiency by improving the quality of the reconstructed image. Likewise, deep neural network techniques applied to intra prediction and encoding are used together with the existing intra prediction tool to improve the compression efficiency by increasing the prediction accuracy or adding a new intra coding process.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.40 no.1
• /
• pp.1-8
• /
• 2016

In this study, we propose a control algorithm for Inertially Stabilized Platforms (ISP), which combines Disturbance Observer (DOB) with conventional proportional integral derivative (PID) control algorithm. A single axis ISP system was constructed using a direct drive motor. The joint friction was modeled as a nonlinear function of joint speed while the accuracy of the model was verified through experiments and simulation. In addition, various Q-filters, which have different orders and relative degrees of freedom (DOF), were implemented. The stability and performance of the ISP were compared through experimental study. The performance of the proposed PID-plus-DOB algorithm was compared with the experimental results of the conventional double loop PID control under artificial vehicle motion provided motion simulator with six DOF.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.39 no.3
• /
• pp.1-7
• /
• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.11
• /
• pp.1-8
• /
• 2007

A wideband continuous-time sigma delta modulator for wireless application is implemented in 130nm CMOS. The SNR for small input signal is improved using a proposed adaptive quantizer which can effectively scale the quantization level. The modulator comprises a second-order loop filter for low power consumption, 4-bit quantizer and DAC for low jitter sensitivity and high linearity. Designed circuit achieves peak SNR of 51.36B with 10MHz signal Bandwidth and 320MHz sampling frequency dissipating 30mW.

• Journal of Electrical Engineering and Technology
• /
• v.11 no.6
• /
• pp.1664-1673
• /
• 2016

Lithium rechargeable cells are used in many industrial applications, because they have high energy density and high power density. For an effective use of these lithium cells, it is essential to build a reliable battery management system (BMS). Therefore, the state of charge (SOC) estimation is one of the most important techniques used in the BMS. An appropriate modeling of the battery characteristics and an accurate algorithm to correct the modeling errors in accordance with the simplified model are required for practical SOC estimation. In order to implement these issues, this approach presents the comparative analysis of the SOC estimation performance using equivalent electrical circuit modeling (EECM) and noise suppression technique (NST) in three representative $LiCoO_2/LiFePO_4/LiNiMnCoO_2$ cells extensively applied in electric vehicles (EVs), hybrid electric vehicles (HEVs) and energy storage system (ESS) applications. Depending on the difference between some EECMs according to the number of RC-ladders and NST, the SOC estimation performances based on the extended Kalman filter (EKF) algorithm are compared. Additionally, in order to increase the accuracy of the EECM of the $LiFePO_4$ cell, a minor loop trajectory for proper OCV parameterization is applied to the SOC estimation for the comparison of the performances among the compared to SOC estimation performance.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.2
• /
• pp.391-396
• /
• 2013

In this paper, for HEVC decoding, an SAO hardware design with less processing time and reduced area is proposed. The proposed SAO hardware architecture introduces the design processing $8{\times}8$ CU to reduce the hardware area and uses internal registers to support $64{\times}64$ CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC $0.18{\mu}m$ library, the gate area is 30.7k and the maximum frequency is 250MHz. The proposed SAO hardware architecture can process the decode of a macroblock in 64 cycles.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.5
• /
• pp.1120-1128
• /
• 2004

In this paper, we has designed and implemented Up-converter for K-band with high IMD3 performance using balanced power amplifier. It is consisted of PA module and, Local Oscillator module with reject Filter, mixer module and If block, and Up-converter has a local loop path to decide whether it operate or not and has the sensing port to inspect output power level. According to the power budget of designed Up-converter, K-band balanced power amplifier was fabricated by commercial MMIC. Measurement results of up-converter show about 40dB Gain, PldB of 29dBm and OIP3 was 38.25dBm, that is good performance compared to power budgets. We has adjusted gate voltage of MMIC to control more than 30 dB gain. This up-converter was used in transceiver for PTP and PTMP, and applied to digital communication system that use QAM and QPSK modulation.