• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.11a
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• pp.10-11
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• 2014

In a 2-dimensional (2D) Discrete Cosine Transform (DCT) hardware, a significant fraction of the total hardware area is contributed by the combinational logic used to perform 1-dimensional (2D) transform. The size of the non-combinational logic i.e. the transpose memory is dictated by the size of the largest transform supported. Hence, the optimization of hardware area is performed mainly for 1D-transform combinational logic. This paper demonstrates the use of Multiple Constant Multiplication (MCM) algorithm to reduce the combinational logic area. Partial optimizations are also described for the cases where the direct use of MCM algorithm doesn't meet the timing constraint. Experimental results show that 46% improvement in gate count is achieved for 32 point 1D DCT transform logic after using MCM optimization.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.1
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• pp.45-50
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• 2001

With increasing complexity of digital logic circuits, fast and accurate verification of functional behaviour becomes most critical bottleneck in meeting time-to-market requirement. This paper presents several techniques for accelerating a cycle-based logic simulation. The acceleration techniques include parallel pattern logic evaluation, circuit size reduction, and the partition of feedback loops in sequential circuits. Among all, the circuit size reduction plays a critical role in maximizing logic simulation speedup by reducing 50% of entire circuit nodes on the average. These techniques are incorporated into a levelized table-driven logic simulation system rather than a compiled-code simulation algorithm. Finally, experimental results are given to demonstrate the effectiveness of the proposed acceleration techniques. Experimental results show more than 27 times performance improvement over single pattern levelized logic simulation.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.3
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• pp.205-212
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• 2012

This paper proposes the fuzzy logic based variable step-size MPPT (Maximum Power Point Tracking) method for the stability at the steady state and the improvement of the transient response in the wind power system. If the change value of duty ratio is set on stability of the steady state, MPPT control traces to maximum power point slowly. And if the change value is set on improvement of the transient response, the system output oscillates at the maximum power point. By adjusting the step size with fuzzy logic, it can be improved the MPPT response speed and stability at steady state when MPPT control is performed to track the maximum power point. The effectiveness of the proposed method has been verified by simulations and experimental results.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.993-996
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• 1993

This paper addresses the structure and its associated learning algorithms of a feedforward multi-layered connectionist network, which has distributed learning abilities, for realizing the basic elements and functions of a traditional fuzzy logic controller. The proposed neural-network-based fuzzy logic control system (NN-FLCS) can be contrasted with the traditional fuzzy logic control system in their network structure and learning ability. An on-line supervised structure/parameter learning algorithm dynamic learning algorithm can find proper fuzzy logic rules, membership functions, and the size of output fuzzy partitions simultaneously. Next, a Reinforcement Neural-Network-Based Fuzzy Logic Control System (RNN-FLCS) is proposed which consists of two closely integrated Neural-Network-Based Fuzzy Logic Controllers (NN-FLCS) for solving various reinforcement learning problems in fuzzy logic systems. One NN-FLC functions as a fuzzy predictor and the other as a fuzzy controller. As ociated with the proposed RNN-FLCS is the reinforcement structure/parameter learning algorithm which dynamically determines the proper network size, connections, and parameters of the RNN-FLCS through an external reinforcement signal. Furthermore, learning can proceed even in the period without any external reinforcement feedback.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2001.12a
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• pp.87-90
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• 2001

This paper is concerned with the estimation of a wafer part in grasping system. The estimation of a wafer size in grasping system is very important because a wafer must be placed in accurate position. The accurate information of a wafer size should be forward to Robot in order to place a wafer in accurate position. So in this paper, we decide the size of a wafer with Fuzzy Logic and consider the possibility of this method by simulation.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1996.04a
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• pp.502-504
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• 1996

Plate(후판) design은 수요가 주문시 지정size(두께, 폭)로 부터 당사 압연 process를 거치면서 발생하는 지시대비 실적간의 차이를 보정하여 최종적으로 산출하게 되며, 이러한 과정은 제품생산시 size 부족으로 인한 불량 발생을 방지하는데 그 목적이 있다. Process진행중 size실적은 .gamma.-ray등 각종 측정기기로 부터 자동 측정되며 이는 process computer로 부터 main computer로 일별 전송되어 3개월 동안 조업관리 DATA BASE에 누적관리되고 있다. 본 연구는 이러한 조업실적을 근거로 제조과정에서 발생하는 size오차를 probability theory과 MULTI-REGRESSION 기법을 적용하여 DESIGN LOGIC을 개발, 제품 실수율을 향상하는데 그 목적이 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1613-1621
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• 1997

Many studies on internal data expression to process logic functions efficiently on computer have been doing actively. In this paper, we propose an efficient logic function manipulation system made on the Objected-Oriented manner, where Binary Decision Diagrams(BDD's) are adopted for internal data espressionof logic functions. Thus it is easy to make BDD's presenting combinational problems. Also, we propose a method of applying filtering function for reducing the size of BDD's instead of attributed bits, and add it to the mainpultion system. As a resutls, the space of address is expanded so that the number of node that can be used in the mainpulation system is increased up to 2/sup 27/. Finally, we apply the implemented system to One-Shot state assignment problems of asynchronous sequential circuits and show that it is efficient for the filtering method to reduce the size of BDD's.

• The Journal of the Acoustical Society of Korea
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• v.23 no.4
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• pp.296-302
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• 2004

Acoustic experiments are performed for a seafloor classification from 19 May to 25 May 2003. The six different sites of bottom composition are settled and the bottom reflection losses with frequencies (30, 50, 80. 100, 120 kHz) are measured. Sediment samples were collected using gravity core and the sample was extracted for grain size analysis. The fuzzy logic is used to classify the seabed. In the fuzzy logic. Bottom 1083 model of frequency dependence is used as the input membership functions and the output membership functions are composed of the Wentworth grain size of the bottom. The possibility of the seafloor classification is verified comparing the inversed mean grain size using fuzzy logic with the results of the coring.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.117-124
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• 1993

In this paper we propose a new thchnology mapping algorithm for multiplexer-based FPGA's The algorithm consists of three phases` First, it converts the logic functions and the basic logic mocule into BDD's. Second. it covers the logic function with the basic logic modules. Lastly, it reduces the number of basic logic modules used to implement the logic function after going through cell merging procedure. The binate selection is employed to determine the order of input variables of the logic function to constructs the balanced BDD with low level. That enables us to constructs the circuit that has small size and delay time. Technology mapping algorithm of previous work used one basic logic module to implement a two-input or three-input function in logic functions. The algorithm proposed here merges almost all pairs of two-input and three-input functions that occupy one basic logic module. and improves the mapping results. We show the effectiveness of the algorithm by comparing the results of our experiments with those of previous systems.

• Journal of the Optical Society of Korea
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• v.17 no.5
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• pp.362-370
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• 2013

In this paper, we propose a novel optical implementation of a 3DES algorithm based on dual XOR logic operations for a cryptographic system. In the schematic architecture, the optical 3DES system consists of dual XOR logic operations, where XOR logic operation is implemented by using a free-space interconnected optical logic gate method. The main point in the proposed 3DES method is to make a higher secure cryptosystem, which is acquired by encrypting an individual private key separately, and this encrypted private key is used to decrypt the plain text from the cipher text. Schematically, the proposed optical configuration of this cryptosystem can be used for the decryption process as well. The major advantage of this optical method is that vast 2-D data can be processed in parallel very quickly regardless of data size. The proposed scheme can be applied to watermark authentication and can also be applied to the OTP encryption if every different private key is created and used for encryption only once. When a security key has data of $512{\times}256$ pixels in size, our proposed method performs 2,048 DES blocks or 1,024 3DES blocks cipher in this paper. Besides, because the key length is equal to $512{\times}256$ bits, $2^{512{\times}256}$ attempts are required to find the correct key. Numerical simulations show the results to be carried out encryption and decryption successfully with the proposed 3DES algorithm.