• Proceedings of the KSR Conference
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• 2000.05a
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• pp.261-268
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• 2000

The purpose of interlocking system was to prevent the route for a train being set up and its protecting signal cleared if there was already another, conflicting route set up and the protecting signal for that route cleared. Recently, the computer based control systems instead of conventional relays circuitry are widely used to industrial systems, therefore, interlocking system are rapidly changing from relay interlocking system to computer controlled interlocking system that control requirements of interlocking at junctions using electronic circuits. However, the reliability of interlocking logic for those systems are harder to demonstrate than in traditional relays circuitry because the faults or errors can not be analyzed and predicted to those systems, In this paper, by examine checking technique of computer controlled interlocking system, we will to acquire interlocking inspection algorithm and method for computer controlled interlocking system

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.135-138
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• 2001

This paper presents micro step driving method using VHDL(Very high speed integrated circuit Hardware Description Language) which can configure CPLD(Complex Programmable Logic Device). Using VHDL which can do abstractive programming is similar to high level language. The whole block divided into five parts with freq. divide part, saw-tooth wave generation part, sine-cosine wave generation part, comparative part, out part. In the result of this study, peripheral circuits are to be simple and using LPM(Library of Parameterized Modules) is more easily to configure circuit. It is easy to verify and implement by using VHDL. To subdivide one natural step, we confirm that using micro step driver is expected that the rotor motion is stepless very smooth.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.3
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• pp.147-152
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• 1985

The error-trapping decoder is constructed for the (7, 3) Reed-Solomon code. The syndrome resister is constructed with the encoder and the substanial test logic circuits. The element of GF(8) is represented by the triple D-flip-floops. The hardware is constructed. And it is controlled by the micro computer(Apple II). The time for the encoding and the decoding were $350\musecs and 910u secs respectively. The experimental results show that the two symbol errors were corrected and 4-bit-binary-burst errors were also corrected.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2490-2492
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• 2001

According to the appearance of various virtual websites using multimedia technologies for engineering education, the internet applications in engineering education have drawn much interests. But unidirectional communication, simple text/image-based webpages and tedious learning process without motivation etc. have made the lowering of educational efficiency in cyberspace. Thus, to cope with these difficulties this paper presents a web-based educational Java applets for understanding the principles or conceptions of digital logic systems. The proposed Java applets provides the improved learning methods which can enhance the interests of learners. The results of this paper can be widely used to improve the efficiency of cyberlectures in the cyber university. Several sample Java applets are illustrated to show the validity of the proposed learning method.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2006.05a
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• pp.407-409
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• 2006

This paper presents the methods of designing the control circuits for a Class D amplifier to have a peak performance. The proposed approach is based on the three functional components - a carrier generator, a feedback circuit and a dead-time circuit. First the analog signal is applied to the controller, which outputs the 3 level PWM waveform. The controller used for this experiment is made of the operational amplifier and the logic circuit. The experimental results show that the control circuit performs with satisfaction and its output is proportional to input audio signal, providing a satisfactory 3 level PWM pattern. From this design methodology, by implementing a proposed control circuit we can achieve the efficient Class D amplifier using the half-bridge, full-bridge or push-pull topology at the output stage.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.30 no.1
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• pp.79-86
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• 2016

In this paper, we propose a current-driven synchronous rectifier driver circuit for LLC resonant half-bridge converters. The proposed driver circuit detects a relatively low current in the primary side of the transformer although a large current is flowing in the secondary side. Due to this feature, the driver circuit has a simple circuit structure and stabilizes the switching operation with a logic-level switching voltages for the synchronous rectifier. The operation and performance of the proposed driver circuit are confirmed with a prototype of 1kW class LLC resonant half-bridge converter. The experimental results proved that the proposed synchronous rectifier driver method improves the power conversion efficiency by around 1% and reduces the internal power loss by 17W.

• Proceedings of the KAIS Fall Conference
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• 2007.11a
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• pp.78-80
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• 2007

According to the development of VLSI integration technology and getting bigger the circuit size, it is a significant problem to verify systemized circuit. The faster and more accurate verification has very significant meaning in the field of electronic industry because it can yield the product comparably faster and reduce the trial and errors. In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

• Journal of the Optical Society of Korea
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• v.16 no.4
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• pp.401-408
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• 2012

The amplitude error of phase modulator used in closed-loop fiber optic gyroscope has occurred by the temperature dependency of the electro-optic coefficient, and also can be due to the square-wave dither signal which is generally applied for eliminating the deadzone. This error can cause bias drift and scale factor error. This paper analyzes the temperature dependency of the modulation amplitude and the relationship with the scale factor of the gyroscope, and deals with an amplitude control method. The error calculation logic considering the dither signal is implemented on the signal processing module. The result of experiments from a prototype gyroscope shows the effect of the modulation amplitude control and a considerable improvement on performances.

• ETRI Journal
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• v.44 no.3
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• pp.491-503
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• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.