• IEIE Transactions on Smart Processing and Computing
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• v.2 no.4
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• pp.248-254
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• 2013

The size and power consumption of digital circuits including the dimming circuit part will increase for high-performance solid state lighting (SSL) systems in the future. This study examined the low-power consumption of adiabatic dynamic CMOS logic (ADCL) due to the principles of adiabatic charging. Furthermore, the designed low-power ADCL digital pulse width modulation (PWM) was optimized for SSL dimming systems. For this purpose, an ADCL digital 3-bit PWM was optimized in two steps. In the first step, the architecture of the ADCL digital 3-bit PWM was miniaturized. In the second step, the clock cut-off circuit was designed and added to the ADCL PWM. As a result, compared to the original configuration, 60 transistors and 15 capacitors of ADCL digital 3-bit PWM were reduced for miniaturization. Moreover, the clock cut-off circuit, which controls wake-up and sleep mode of ADCL D-FFs, was designed. The power consumption of an optimized ADCL digital PWM for all bit patterns decreased by 54 %.

• Journal of Electrical Engineering and Technology
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• v.6 no.5
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• pp.595-604
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• 2011

A three-phase three-level shunt active filter controlled by fuzzy logic current controller which can compensate current harmonics generated by nonlinear loads is presented. Three-level inverters and fuzzy controllers have been successfully employed in several power electronic applications these past years. To improve the conventional pwm controller performance, a new control scheme based on fuzzy current controller is adopted for three-level (NPC) shunt active filter. The scheme is designed to improve compensation capability of APF by adjusting the current error using a fuzzy rule. The inverter current reference signals required to compensate harmonic currents use the synchronous reference detection method. This technique is easy to implement and achieves good results. To maintain the dc voltage across capacitor constant and reduce inverter losses, a proportional integral voltage controller is used. The simulation of global system control and power circuits is performed using Matlab-Simulink and SimPowerSystem toolbox. The results obtained in transient and steady states under various operating conditions show the effectiveness of the proposed shunt active filter based on fuzzy current controller compared to the conventional scheme.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.4
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• pp.204-212
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• 2001

본 논문에서는 조합논리회로의 테스트 컴팩션을 위한 두 가지 효율적인 알고리즘을 제안한다. 제안된 알고리즘들은 각각 동적인 컴팩션 기법과 정적인 컴팩션 기법을 사용하고 있으며, 실험을 위해 기존의 ATPG시스템인 ATALANTA에 통합 구현하였다. ISCAS85와 ISCAS89(완전스캔 버전) 벤치마크 회로에 대한 실험에서 본 시스템은 기존에 발표된 다른 컴팩션 알고리즘에 비하여 보다 작은 테스트 집합을 보다 빠르게 생성하였으며, 실험 결과를 통하여 제안된 알고리즘들의 유효성을 입증할 수가 있었다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1021-1024
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• 1998

Computer-aided design of VLSI circuits is usually carried out in three synthesis steps; high-level synthesis, logic synthesis and layout synthesis. Each synthesis step is further kroken into a few optimization problems. In this paper we study the area minimization problem in floorplanning(also known as the floorplan sizing problem). We propose the area minimization algorithms for general floorplans.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.759-762
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• 1998

In this paper, a SL-DCVSL (static latched differential cascode voltage switch logic) circuit for the asynchronous pipeline is proposed. The proposed SL-DCVSL circuit is a slightly modified version of the DCVSL circuit, and used to improve the storage capability of the precharged functional blocks. The proposed SL-DCVSL has more robust storage characteristics compared to the conventional LDCVSL (latched DCVSL〔2〕). The operation of the proposed circuit is verified by simulating the asynchronous FIFO (First-In First-Out) structure.

• Proceedings of the KAIS Fall Conference
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• 2009.12a
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• pp.636-639
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• 2009

In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.141-145
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• 1998

This paper CMOS full adder design method based on carry-propagation-free addition trees and a circuit technique, so called multiple-valued current-mode (MVCM) circuits. The carry-paopagation-free addition method uses a redundant digit sets called redundant positive-digit number representations. The carry-propagation-free addition is by three steps, and the adder can be designed directly and efficiently from the algorithm using MVCM circuit. We demonstrate the effectiveness of the proposed method through simulation(SPICE).

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.392-395
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• 1999

The state assignment for a finite state machine greatly affects the delay, area, and testabilities of the sequential circuits. In order to minimize the dependencies among state variables, therefore possibly to reduce the length and number of feedback cycles, a new state assignment technique based on m-block partition is introduced in this paper. After the completion of state assignment and logic synthesis, partial scan design is performed to choose minimal number of scan flip-flops. Experiment shows drastic improvement in testabilities while preserving low area and delay overhead.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.5
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• pp.661-670
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• 1995

This paper presents a fast massively parallel automatic test pattern generator for digital combinational logic circuits using neural networks. Automatic test pattern generation neural network(ATPGNN) evolves its state to a stable local minima by exchanging messages among neural network modules. In preprocessing phase, we calculate the essential assignments for the stuck-at faults in fault list by adopting dominator concept. It makes more neurons be fixed and the system speed up. Consequently. fast test pattern generation is achieved. Test patterns for stuck-open faults are generated through getting initialization patterns for the obtained stuck-at faults in the corresponding ATPGNN.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1963-1967
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• 1996

This paper describes the analysis, design, and silicon-fabrication of a fluidic proportional amplifier, which is the most important element of fluidic logic circuits. First, FEM(finite element method) analyses were performed, using the Fluent computational fluid dynamics program, and design geometries were optimized. Then, a $40\;{\mu}m$-deep amplifier was fabricated in silicon using anisotropic dry etching.