Journal of KIISE:Computer Systems and Theory (한국정보과학회논문지:시스템및이론)

Korean Institute of Information Scientists and Engineers (한국정보과학회)
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Efficient Test Compaction Algorithms for Combinational Logic Circuits

조합논리회로를 위한 효율적인 테스트 컴팩션 알고리즘

  • Kim, Yun-Hong (Dept.of Computer Information Communication Engineering, Sangmyung University)
  • 김윤홍 (상명대학교 컴퓨터정보통신공학부)
  • Published : 2001.04.01
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Abstract

본 논문에서는 조합논리회로의 테스트 컴팩션을 위한 두 가지 효율적인 알고리즘을 제안한다. 제안된 알고리즘들은 각각 동적인 컴팩션 기법과 정적인 컴팩션 기법을 사용하고 있으며, 실험을 위해 기존의 ATPG시스템인 ATALANTA에 통합 구현하였다. ISCAS85와 ISCAS89(완전스캔 버전) 벤치마크 회로에 대한 실험에서 본 시스템은 기존에 발표된 다른 컴팩션 알고리즘에 비하여 보다 작은 테스트 집합을 보다 빠르게 생성하였으며, 실험 결과를 통하여 제안된 알고리즘들의 유효성을 입증할 수가 있었다.

Keywords

References

  1. J. P. Roth, 'Diagnosis of automata failures: A calculus and a method,' IBM J. Res. Develop., vol. 10, pp.278-291, July 1966
  2. P. Goel, 'Implicit enumeration algorithm to generate Tests for Combinational Logic Circuits,' IEEE Trans. Comput, vol. C-30, pp.215-222, Mar. 1981 https://doi.org/10.1109/TC.1981.1675757
  3. H. Fujiwara and T. Shimono, 'On the acceleration of test generation algorithms,' IEEE Trans. Comput, vol. C-32, no.12, pp.1137-1144, Dec. 1983 https://doi.org/10.1109/TC.1983.1676174
  4. M. Schulz, E. Trischler, and T. Sarfert, 'SOCRATES: A highly efficient automatic test pattern generation system,' IEEE Trans. Computer-Aided Design., vol. 7, pp.126-137, Jan. 1988 https://doi.org/10.1109/43.3140
  5. B. Krishnamurthy and S. B. Akers, 'On the complexity of estimating the size of a test set,' IEEE Trans. Comput., vol. C-33, no.8, pp.750-753, Aug. 1984
  6. G. Tromp, 'Minimal test sets for combinational circuits,' in Proc. IEEE Int. Test Conf., pp.204-209 Oct.1991
  7. Y. Matsunaga, 'MINT-An exact algorithm-, for finding minimum test sets,' IEICE Trans. Fundamentals, vol. E76-A, pp.1652-1658, Oct. 1993
  8. J. Chang and C. Lin, 'Test Set Compaction for Combinational Circuits,' IEEE Trans. Comput.,' vol. 14, no.11, pp.1370-1378, Nov, 1995 https://doi.org/10.1109/43.469663
  9. P. Goel and B. C. Rosales, 'Test generation & dynamic compaction of tests,' in Dig. Papers Test Conf., pp.189-192, Oct. 1979
  10. I. Pomeranz, L. N. Reddy, and S. M. Reddy, 'COMPACTEST: A method to generate compact test sets for combinational circuits,' in Proc. IEEE Int. Test Conf., pp.194-203, Oct. 1991
  11. L. N. Reddy, I. Pomeranz, and S. M. Redely, 'ROTCO: A reverse order test compaction technique,' in Proc. 1992 Euro-ASIC Conf., pp.189-194, 1992 https://doi.org/10.1109/EUASIC.1992.228026
  12. S. Kajihara, I. Pomeranz, K. Kinoshita and S. M. Reddy, 'Cost-Effective of Minimal Test sets for Stuck-at Faults in Combinational Logic Circuits,' IEEE Trans. on Computer-Aided Design, pp.1496-1504, Dec. 1995 https://doi.org/10.1109/43.476580
  13. H. K. Lee and D. S. Ha, 'On the Generation of Test Patterns for Combinational Circuits,' Technical Report No. 12_93, Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University
  14. F. Brglez and H. Fujiwara, 'A neutral netlist of 10 combinatorial benchmark circuits and a target translator in Fortran,' in Proc. Int. Symp. Circuits Syst, June 1985
  15. F. Brglez, D. Bryan, and K. Kozmihski, 'Combinational Profiles of Sequential Benchmark Circuits,' in Proc. the Int. Symp. on Circuits and Systems, pp.1929-1934. May 1989 https://doi.org/10.1109/ISCAS.1989.100747
  16. S. B. Akers, C. Joseph, and B. Krishnamurthy, 'On the Role of Independent Fault Sets in the Generation of Minimal Test Sets,' in Proc. IEEE Int. Test conf., pp.204-209, Oct. 1991
  17. M. S. Hsiao, E. M. Rudnick, and J. H. Patel, 'Fast algorithms for static compaction of sequential circuit test vectors,' in Proc. IEEE VLSI Test Symp., pp.188-195, Apr. 1997 https://doi.org/10.1109/VTEST.1997.600260
  18. R. Guo, I. Pomeranz, and S. M. Reddy, 'Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration,' in Proc. Design, Automation, and Test in Europe(DATE) Conf., pp.583-587, Feb. 1998