• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.1
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• pp.26-28
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• 2004

In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

• The Transactions of the Korea Information Processing Society
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• v.3 no.2
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• pp.315-326
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• 1996

As the complexity of VLSI circuits has increased, a lot of simulation time for verifying their correctness has been required. This paper presents efficient parallelel logic simulation protocols, data structures, algorithms to implement fast logic simulation on SIMD parallel processing computers. The performance results of the presented schemes on CM-2 are given and analyzed.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2802-2803
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• 2000

In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small Quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

• Journal of Drive and Control
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• v.13 no.2
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• pp.51-58
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• 2016

The present study deals with the issue of clamping force control of an injection molding machine using 2-way cartridge valve based logic circuit. The operating principle for the cartridge valve is described with its construction and static opening behavior. Basic module circuits are designed first and analysed according to the basic functions. Then they are combined with a virtual design model for the clamping mechanism to simulate the control performance of the overall system. The backlash inherent in the mechanism is considered while evaluating the time-delay in the process of clamping force build-up. The effects of a couple of design parameters in backlash, i.e., interval and stiffness have been demonstrated in the time-domain.

• Progress in Superconductivity and Cryogenics
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• v.8 no.1
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• pp.26-28
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• 2006

The development technique of digital logic using CMOS device is close reached several limitations These make technical needs that are ultra high speed superconductive systems based on CMOS silicon digital computing technique. Comparing digital logic based on silicon CMOS, the computing technique based on ultra high speed superconductive systems has many advantages which are ultra low power consumption, ultra high operation speed. etc. It is estimated that features like these increasingly improve the possibility of ultra low power and ultra superconductive systems. In this paper digital logics of current CMOS technique and RSFQ superconductive technique are compared with and analyzed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.295-308
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• 1986

This paper presents a method of constructing multiple-valued logic functions based on Galois field. The proposed algorithm assigns all elements in GF(2**m) to bit codes that are easily converted binary. We have constructed an adder and a multiplier using a multiplexer after bit code operation (addition, multiplication) that is performed among elements on GF(2**m) obtained from the algorithm. In constructing a generalized multiple-valued logic functions, states are first minimized with a state-transition diagram, and then the circuits using PLA widely used in VLSI design for single and multiple input-output are realized.

• Journal of Advanced Marine Engineering and Technology
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• v.33 no.8
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• pp.1246-1253
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• 2009

This paper presents derived a calculating form of fuzzy inference, based on decomposition of $\alpha$-level sets. Based on the calculating form it is propose that fuzzy logic circuits of PI+PD controller are a body from fuzzy inference to defuzzificaion in cases where the command variable u directly is generated PWM. The effect of quantization on $\alpha$-levels is investigated. with input/out characteristics of fuzzy controller by simulation. It is concluded that 4 quantization levels are sufficient result for fuzzy control performance of DC servo system. Simulation and experimental results demonstrated that the hardware implementation of the proposed controller can successfully provide good performance on the position control of DC servo system.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.349-352
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• 2002

This paper describes a design of a 1bit Carry Propagate Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1bit CPFA/S is compared with that of the CMOS 1bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/23 as low as that of the CMOS circuits. The transistors count, propagation-delay tittle and energy dissipation of the ADCL 4bit CPFA/S are compared with those of the ADCL 4bit Carry Propagate Adder/Subtracter (CPA/S). The transistors count and propagation-delay tittle are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1bit CPFA/S fabricated in a $1.21mutextrm{m}$ CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1㎒.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.640-648
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• 2014

Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS'89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.131-134
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• 2002

In this work, we have developed a systematic way of utilizing the basic design tools for superconductive electronics. This include WRSPICE, XIC, margin program, and L-meter. Since the high performance analog-to- digital converter can be built with Rapid Single Flux Quantum (RSFQ) logic circuits the development of superconductive analog-to-digital converter has attracted a lot of interests as one of the most prospective area of the application of Josephson Junction technology. One of the main advantages in using Rapid Single Flux Quantum logic in the analog-to-digital converter is the low voltage output from the Josephson junction switching, and hence the high resolution. To design an 1-bit analog-digital converter, first we have used XIC tool to compose a circuit schematic, and then studied the operational principle of the circuit with WRSPICE tool. Through this process, we obtained the proper circuit diagram of an 1-bit analog-digital converter circuit. Based on this circuit we performed margin calculations of the designed circuits and optimized circuit parameters. The optimized circuit was laid out as a mask drawing. Inductance values of the circuit layout were calculated with L-meter. Circuit inductors were adjusted according to these calculations and the final layout was obtained.