• 센서학회지
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• 제23권2호
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• pp.73-81
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• 2014

Silicon PIN diode radiation sensors and CMOS readout circuits were designed and fabricated in this study. The PIN diodes were fabricated using a 380-${\mu}m$-thick 4-inch n+ Si (111) wafer containing a $2-k{\Omega}{\cdot}cm$ n- thin epitaxial layer. CMOS readout circuits employed the driving and signal processes in a radiation sensor were mixed with digital logic and analog input circuits. The primary functions of readout circuits are amplification of sensor signals and the generation of the alarm signals when radiation events occur. The radiation sensors and CMOS readout circuits were fabricated in the Institute of Semiconductor Fusion Technology (ISFT) semiconductor fabrication facilities located in Kyungpook National University. The performance of the readout circuit combined with the Si PIN diode sensor was demonstrated.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.383-386
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• 2000

There are some variations in quiescent supply current or TTL SSIs. Thus, some variations in quiescent supply current of logic circuits made of TTL SSIs will be generated. The variations make it difficult to apply supply current test methods to tests of TTL circuits. In this paper, in order to examine the applicability to R circuits, fault coverages of a supply current test method for open faults in some ISCAS-85 benchmark circuits are evaluated, Which are made of TTL LS-type SSIs. The experimental results shows that if SSIs are used for implementation having the variation of quiescent supply current within 1%, supply current test methods are applicable for the tests.

• Progress in Superconductivity
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• 제3권1호
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• pp.17-22
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• 2001

Practical implementation of the SFQ technology in most application requires more than single-chip-level circuit complexity. Multiple chips have to be integrated with a technology that is reliable at cryogenic temperatures and supports an inter-chip data transmission speed of tens of GHz. In this work, we have studied two basic issues in building large RSFQ circuits. The first is the reliable inter-chip SFQ pulse transfer technique using Multi-Chip-Module (MCM) technology. By noting that the energy contained in an SFQ pulse is less than an attojoule, it is not very surprising that the direct transmission of a single SFQ pulse through MCM solder bump connectors can be difficult and an innovative technique is needed. The second is the recycling of the bias currents. Since RSFQ circuits are dc current biased the large RSFQ circuits need serial biasing to reduce the total amount of current input to the circuit.

• Journal of the Optical Society of Korea
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• 제16권4호
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• pp.432-442
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• 2012

In this paper, we propose, analyze and simulate the performances of some new plasmonic logic gates in two dimensional plasmonic waveguides with nanodisk resonators, using the numerical method of finite difference time domain (FDTD). These gates, including XOR, XNOR, NAND, and NOT, can provide the highly integrated optical logic circuits. Also, by cascading and combining these basic logic gates, any logic operation can be realized. These devices can be utilized significantly in optical processing and telecommunication devices.

• 전자공학회논문지C
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• 제36C권10호
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• pp.29-38
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• 1999

본 논문은 조합 논리회로에서의 시험 불가능한 결함(untestable faults)을 확인하는 새로운 알고리즘 RICP(Redundancy Identification using Critical-pair Paths)를 제시한다. 조합 논리회로에서의 시험 불가능 결합은 회로의 과잉(redundancy)에 의해서 발생한다. 회로의 과잉은 팬 아웃 스템(fanout stem)과 재결집 게이트(reconvergent gate)의 영역을 분석함으로서 찾을 수 있다. 시험 불가능한 결함들은 임계 경로의 확장된 개념인 임계-쌍 경로를 이용하여 스템 영역을 분석함으로써 확인되어진다. RICP 알고리즘이 FIRE(Fault Independent REdundancy identification) 알고리즘보다 효율적이라는 것을 보여준다. ISCAS85 벤치마크 테스트 회로에 대한 두 알고리즘의 실험 결과를 비교하였다

• 대한전자공학회논문지
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• 제26권1호
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• pp.98-103
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• 1989

본 논문에서는 게이트 레벨에서 논리 최적화를 하기 위한, 새로운 시스템을 제안한다. 본 시스템은 회로의 일부분을 간략화된 등가회로로 대치하는 local transformation을 rule로 표현한 rule-based 시스템이다. 본 시스템에서는 효율적인 패턴매칭을 위해, 'rule의 일반화'와 '국소최적화'를 제안한다. Rule의 일반화는 패턴매칭시 회로탐색을 줄이기 위해 사용되며, 국소최적화는 불필요한 회로탐색을 배제하기 위해 사용된다. 또한, 불필요한 패턴매칭 시도를 줄이기 위해, 회로 패턴의 매칭순서를 rule 기술에 포함시킨다. 또한, 본 시스템을 하드웨어 컴파일러에 의해 생성된 논리회로 최적화에 적용하여, 그 효용성을 보인다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.168-176
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• 2015

Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS'89 benchmark circuits show that our method is more accurate and efficient than previous methods.

• 한국군사과학기술학회지
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• 제17권4호
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• pp.404-412
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• 2014

We proposed a design method for squib current supply & interlock circuits in guided-missile fire control systems. In order to design squib current supply circuits, various missile squib loads including line resistance and squib devices have to be considered in advance minimizing probability of redesign of circuits and reducing the development cost by implementing the most proper squib current supply circuit. Also, we presented a hardware interlock logic instead of the commonly used software safety logic to improve the safety of guided-missile fire control systems. The proposed squib interlock circuit enhances safety requirements of guided-missile fire control systems. We confirmed that simulation and measurement results of the proposed design method are the same as theoretical analysis results.

• 정보처리학회논문지A
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• 제9A권3호
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• pp.271-280
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• 2002

본 논문에서는 Perfect Shuffle 기법과 Kronecker 곱에 의한 다치 신호처리회로의 입출력 상호연결에 대하여 논하였고, 다치 신호처리회로의 입출력 상호연결 방법을 이용하여 유한체 GF$(p^m)$상에서 다치 신호처리가 용이한 다치 Reed-Muller 전개식의 회로설계 방법을 제시하였다. 제시된 다치 신호처리회로의 입출력 상호연결 방법은 모듈구조를 기반으로 하여 행렬변환을 이용하면 회로의 가산게이트와 승산게이트를 줄이는데 매우 효과적임을 보인다. GF$(p^m)$상에서 다치 Reed-Muller 전개식에 대한 다치 신호처리회로의 설계는 GF（3）상의 기본 게이트들을 이용하여 다치 Reed-Muller 전개식의 변환행렬과 역변환행렬을 실행하는 기본 셀을 설계하였고, 다치 신호처리회로의 입출력 상호연결 방법을 이용하여 기본 셀들을 상호연결하여 실현하였다. 제안된 다치 신호처리회로는 회선경로 선택의 규칙성, 간단성, 배열의 모듈성과 병렬동작의 특징을 가지므로 VLSI 화에 적합하다

• Progress in Superconductivity
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• 제5권1호
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• pp.21-25
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• 2003

We have designed and simulated an 1-bit ALU (Arithmetic Logic Unit) by using a half adder. An ALU is the part of a computer processor that carries out arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We constructed an 1-bit ALU by using only one half adder and three control switches. We designed the control switches in two ways, dc switch and NDRO (Non Destructive Read Out) switch. We used dc switches because they were simple to use. NDRO pulse switches were used because they can be easily controlled by control signals of SET and RESET and show fast response time. The simulation results showed that designed circuits operate correctly and the circuit minimum margins were ＋/-27%. In this work, we used simulation tools of XIC and WRSPICE. The circuit layouts were also performed. The circuits are being fabricated.