• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.504-511
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• 2003

The property of circuit symmetry has long been applied to the Problem of minimizing the area and timing of multi-level logic circuits. In this paper, we focus on another important design objective, power minimization, utilizing circuit symmetries. First, we analyze and establish the relationship between several types of circuit symmetry and their applicability to reducing power consumption of the circuit, proposing a set of re-synthesis techniques utilizing the symmetries. We derive an algorithm for detecting the symmetries (among the internal signals as well as the primary inputs) on a given circuit implementation. We then propose effective transformation algorithms to minimize power consumption using the symmetry information detected from the circuit. Unlike many other approaches, our transformation algorithm guarantees monotonic improvement in terms of switching activities, which is practically useful in that user can check the intermediate re-synthesized designs in terms of the degree of changes of power, area, timing, and the circuit structure. We have carried out experiments on MCNC benchmark circuits to demonstrate the effectiveness of our algorithm. On average we reduced the power consumption of circuits by 12% with relatively little increase of area and timing.

• Proceedings of the Korean Nuclear Society Conference
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• 1996.05a
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• pp.515-520
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• 1996

Since the conventional Westinghouse DNB (Departure from Nucleate Boiling) protection logic is implemented on analog circuits, the logic must be very simple. However, if the DNB protection logic is implemented in a digital processor, a little bit of complexity can be allowed to increase the thermal (or operation) margin. The Westinghouse OTΔT DNB protection logic heavily restricts the operation region by applying the same logic for a full range of pressure in order to maintain its simplicity. In this work, the different DNB protection logic is used for several regions of pressure. The proposed method is applied to Yonggwang 1&2 nuclear power plants and it is calculated that the improved OTΔT can have 5.07% percent more thermal margin than the conventional OTΔT trip logic.

• The Magazine of the IEIE
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• v.22 no.8
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• pp.98-110
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• 1995

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.54-58
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• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• Proceedings of the KSR Conference
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• 2000.11a
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• pp.652-658
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• 2000

TCMS(Train Control ＆ Management System) control monitor and test the main on-board equipments including propulsion/brake unit by the serial transmission line. TCMS reduces interface circuits and number of train lines by the software logic and utilizing serial communication method. This paper describes the method of powering and braking control by TCMS software logic, and the software logic is verified by running test at Seoul Subway Line＃ 6. By running test result, we can see TCMS successfully control Powering/Braking of train

• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.421-426
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• 2010

This paper presents a method of design the counter using sequential system based on synchronous techniques. For the design the counter, first of all, we derive switching algebras and their operations. Also, we obtain the next-state functions, flip-flop excitations and their input functions from the flip-flop. Then, we propose the algorithm which is a method of implementation of the synchronous sequential digital logic circuits. Finally, we apply proposed the sequential logic based on synchronous techniques to counter.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.9
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• pp.5744-5749
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• 2014

An extraction technique for a common logic expression is an extremely important part of multiple-output logic synthesis. This paper presents a new Boolean extraction technique using an exclusive-OR logic synthesis principle. The logic circuits produced only have AND, OR and NOT gates. Heuristic methods can also be applied to reduce the execution time and the number of literals. The experimental results showed improvements in the literal counts over the previous methods.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.785-788
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• 1993

This paper presents the prototype framework for automated integration of CMOS current-mode fuzzy logic circuits using an intelligent module approach. The library of modules representing the standard fuzzy logic operators was built. These modules were finally used to synthesized sophisticated fuzzy logic units. Fuzzy unit designs were made based upon the results of a newel methodology of the current mirror-based fuzzy logic function synthesis. This methodology is actually incorporated into the presented framework. As an example, the membership function unit was synthesized, simulated, and the final layout was generated using the presented framework. Finally, the fuzzy logic controller unit (FLC) was generated using the proposed framework. Simulation as well as measurement results show unquestionable advantages of the proposed fuzzy logic function integration system over the classical design methodology with respect to the area, relative error and performance.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.10
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• pp.73-80
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• 1995

In this paper, a synthesis tool using matrix operations for designing multi-level Reed Muller circuits is described which has been named as MRM (Multi-level Reed Muller Minimizer). The synthesis method which uses matrix operations has advantages in effectively minimizing chip area, delay optimization and fault detection capability. However, it uses only truth-table type maps for inputs, synthesizing only small circuits. To overcome the weakness, our method accepts two-level description of a logic function. Since the number of cubes in the two-level description is small, the input matrix becomes small and large circuits can be synthesized. To convert two-level representations into multi-level ones, different input patterns are extracted to make a map which can be fed to the matrix operation procedure. Experimental results show better performance than previous methods. The matrix operation method presented in this paper is new to the society of Reed Muller circuits synthesis and provides solid mathematical foundations.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.173-184
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• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.