• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.817-820
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• 2008

Development of computer and internet has permitted cyber education transcending time and space, which escapes traditional classroom. As a result, the study of learner's own leading in Web-based instruction environment can be possible. In order to perform it effectively, suitable helps and advices, called scaffolding, must be offered. In this pater, we select a principle of computer in information technology basic subject of technical high school, and design and implement the web contents that provide the proper scaffolding for learners.

• KSBB Journal
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• v.29 no.4
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• pp.225-231
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• 2014

A microbial fuel cell (MFC) and bioelectrochemical systems are novel bioprocesses which employ exoelectrogenic biofilm on electrode as a biocatalyst for electricity generation and various useful chemical production. Previous reports show that electrogenic biofilms of MFCs are time varying systems and dynamically interactive with the electrically conductive media (carbon paper as terminal electron acceptor). It has been reported that maximum power point tracking (MPPT) method can automatically control load by algorithm so that increase power generation and columbic efficiency. In this study, we developed logic based control strategy for external load resistance by using $LabVIEW^{TM}$ which increases the power production with using flat-plate MFCs and MPPT circuit board. The flat-plate MFCs inoculated with anaerobic digester sludge were stabilized with fixed external resistance from $1000{\Omega}$ to $100{\Omega}$. Automatic load control with MPPT started load from $52{\Omega}$ during 120 hours of operation. MPPT control strategy increased approximately 2.7 times of power production and power density (1.95 mW and $13.02mW/m^3$) compared to the initial values before application of MPPT (0.72 mW and $4.79mW/m^3$).

• School Mathematics
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• v.7 no.4
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• pp.353-373
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• 2005

The purpose of this paper is to analysis the basic network problem which can be applied to the mathematically gifted students in elementary school. Mainly, we discuss didactic transpositions of the double counting principle, the game of sprouts, Eulerian graph problem, and the minimum connector problem. Here the double counting principle is related to the handshaking lemma; in any graph, the sum of all the vertex-degree is equal to the number of edges. The selection of these subjects are based on the viewpoint; to familiar to graph theory, to raise algorithmic thinking, to apply to the real-world problem. The theoretical background of didactic transpositions of these subjects are based on the Polya's mathematical heuristics and Lakatos's philosophy of mathematics; quasi-empirical, proofs and refutations as a logic of mathematical discovery.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1575-1582
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• 1998

Reed-Solomon(RS) code which is especially effective against burst error is studied as a forward error correction technique in this ppaer. The circuits of RS encoder and decoder for ASIC implementation are designed and presented employing modified Euclid's algorithm. The functionalities of the designed circuits are verified though C programs which simulates the circuits over the various errors and erasures. The pipelined circuits using systolic arrays are designed for ASIC realization in VHDL, and verified through the logic simulations. Finally the circuit synthesis of RS encoder and decoder can be achieved.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.11
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• pp.650-656
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• 2003

A high speed Viterbi decoder with a circularly connected 2-dimensional analog processing ceil array Is proposed. The proposed Viterbi .decoder has a 2-dimensional parallel processing structure in which an analog processing cell is placed at each node of a trellis diagram, the output column of the analog processing cells is connected to the decoding column, and thus, the output(last) column becomes a column right before the decoding(first) column. The reference input signal given at a decoding column is propagated to the whole network while Its magnitude is reduced by the amount of a error metric on each branch. The circuit-based decoding is done by adding a trigger signals of same magnitudes to disconnect the path corresponding to logic 0 (or 1) and by observing its effect at an output column (the former column of the decoding column). The proposed Viterbi decoder has advantages in that it is operated with better performance of error correction, has a shorter latency and requires no path memories. The performance of error correction with the proposed Viterbi decoder is tested via the software simulation.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.579-587
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• 2008

Promotion of the line no.2 in Seoul Metro was changing from the existing signaling facilities for ATS(Automatic Train Stop) vehicles to the up-to-date signaling facilities for ATO(Automatic Train Operation). But, in consequence of conducting a trial run after being equipped with the ATO signaling facilities, the matter related to mix-operation with the existing ATS signaling facilities appeared. The operation of the existing ATS signaling system in combination with the ATO signaling system has made improper working related to frequency recognition of the ATS On-board Computerized Equipment. This obstructs operation of a working ATS vehicle. That is, as barring operation of an ATS vehicle that should proceed, it may make the proceeding ATS vehicle stop suddenly and after all, it will cause safety concerns. In this paper, we designed a wayside track occupancy detector that previously prevents improper working related to frequency recognition of the ATS On-board Computerized Equipment by gripping classification and working processes of operating trains throughout transmission of local signaling information from the existing facilities, which does not need to change or replace the existing signaling facilities. Furthermore, we described general characteristics of the wayside track occupancy detector and modeled the IFC(InterFace Contrivance) device and the logical circuit recognizing signal information. Then, we made an application program of PLC(programmable Logic Computer) based on the stated model. We, in relation to data transfer method, used the frame in TCP/IP transfer mode as the standard, and we demonstrated that ATO transmission frequency is intercepted.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.1
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• pp.1-6
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• 2014

In this paper, we propose a CPLD low power algorithm considering the structure. The proposed algorithm is implemented CPLD circuit FC(Feasible Cluster) for generating a problem occurs when the node being split to overcome the area and power consumption can reduce the algorithm. CPLD to configure and limitations of the LE is that the number of OR-terms. FC consists of an OR node is divided into mainly as a way to reduce the power consumption with the highest number of output nodes is divided into a top priority. The highest number of output nodes with the highest number of switching nodes become a cut-point. Division of the node is the number of OR-terms of the number of OR-terms LE is greater than adding the input and output of the inverter converts the AND. Reduce the level, power consumption and area. The proposed algorithm to MCNC logic circuits by applying a synthetic benchmark experimental results of 13% compared to the number of logical blocks decreased. 8% of the power consumption results in a reduced efficiency of the algorithm represented been demonstrated.

• Proceedings of the IEEK Conference
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• summer
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.251-255
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• 2015

In this paper, we propose a fuse controller which is used for storing the optimal value or the correction value for the surrounding product of the IoT applications and it is implemented serial communication circuit using a single pin. Because of the proposed single pin protocol is simpler in the hardware than the conventional $I^2C$ and SPI using two or more pins, it is suitable for the area of small amount of data transmission. The function of the one pin protocol is verified by logic simulation and the FPGA test board and it is fabricated using CMOS 0.35um technology. It is expected to use the IoT product that require the low power consumption and simple hardware.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.152-161
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• 1996

In tis work, a three-stage pipelined A/D converter (ADC) was implemented to obtain 10-bit resolution at a conversion rate of 20 msamples/s for video applications. The ADC consists of three identical stages employing a mid-rise coding technique. The interstage errors such as offsets and clock feedthrough are digitally corrected in digitral logic by one overlapped bit between stages. The proposed ADC is optimized by adopting a unit-capacitor array architecture in the MDAC to improve the differential nonlinearity and the yield. Reduced power dissipation has been achieve dby using low-power latched comparators. The prototype was fabricated in a 0.8$\mu$m p-well CMOS technology. The ADC dissipates 160 mW at a 20 MHz clock rate with a 5 V single supply voltage and occupies a die area of 7 mm$^{2}$(2.7 mm $\times$ 2.6mm) including bonding pads and stand-alone internal bias circuit. The typical differential and integral nonlinarities of the prototype are less than $\pm$ 0.6 LSB and $\pm$ 1 LSB, respectively.