• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.38-49
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• 1997

In this paper, w describe partitioning large circuits into multiple chips on the programmable FPCB for rapid prototyping. FPCBs consists of areas for FPGAs for logic and interconnect components, and the routing topology among them are predetermined. In the partition problem for FPCBs, the number of wires ofr routing among chips is fixed, which is an additonal constraints to the conventional partition problem. In order to deal with such aconstraint properly we first define a new partition problem, so called the topologybased partition problem, and then propose a heuristic method. The heuristic method is based on the simulated annealing and clustering technique. The multi-level tree clustering technique is used to obtain faster and better prtition results. In the experimental results for several test circuits, the restrictions for FPCB were all satisfied and the needed execution time was about twice the modified K-way partition method for large circuits.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.140-148
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• 1993

High Integration ratio of CMOS circuits incredily increases the test cost during the design and fabrication processes because of the FET fault(Stuck-on faults and Stuck-off faults) which are due to the operational characteristics of CMOS circuits. This paper proposes a test generation algorithm for an arbitrarily large CMOS circuit, which can unify the test steps during the design and fabrication procedure and be applied to both static and dynaic circuits. This algorithm uses the logic equations set for the subroutines resulted from arbitrarily dividing the full circuit hierarchically or horizontally. Also it involves a driving procedure from output stage to input stage, in which to drive a test set corresponding to a subcircuit, only the subcircuits connected to that to be driven are used as the driving resource. With this algorithm the test cost for the large circuit such as VLSI can be reduced very much.

• 전기의세계
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• v.29 no.6
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• pp.393-400
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• 1980

It is shown in this paper that it is possible to derive generalized state equations for computation of electrical circults constanining SCR and diode elements. Revankar's binary logic variable method is used for formulation of the state equation of chopper circuit. Advantage of this method is that the state equations can be set up without the exact knowledge of the circuit operaton. The different modes of operation of the circuit are identified by the computer itself. By applying this method, the steady state performances of separately excited chopper-fed dc motor considering the counter electromotive force of the motor are investigated and the results of the computer simulation are presented. There is a satisfactory agreement between the theoretical and experimental results.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3078-3080
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• 2000

In this paper. we designed a high precision Linear DC Motor(LDM) Driver with $120^{\circ}$ commutation method. It was composed of three parts which were divided into Power and Inverter Circuit. Analog Circuit with PWM Generation and Fault Protections. and Logic Circuit. We selected PMAC Controller by Delta Tau Co. for testifying a high accuracy of a designed driver. A high precision driver enhanced a response to changes of velocity and acceleration in motion and improved the accuracy.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.113-116
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• 2003

Confluence buffers and single flux quantum (SFQ) switches are essential components in constructing a high speed superconductive Arithmetic Logic Unit (ALU). In this work, we developed a SFQ confluence buffer and an SFQ switch. It is very important to optimize the circuit parameters of a confluence buffer and an SFQ switch to implement them into an ALU. The confluence buffer that we are currently using has a small bias margin of $\pm$11％. By optimizing it with a Josephson circuit simulator, we improved the design of confluence buffer. Our simulation study showed that we improved bias global margin of 10％ more than the existent confluence buffer. In simulations, the minimal bias margin was $\pm$33％. We also designed, fabricated, and tested an SFQ switch operating in a DC mode. The mask layout used to fabricate the SFQ switch was obtained after circuit optimization. The test results of our SFQ switch showed that it operated correctly and had a reasonably wide margin of $\pm$15％.

• Journal of the Korean Institute of Telematics and Electronics
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• v.3 no.3
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• pp.14-21
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• 1966

In this article, a recording system for nuclear radiation detection by means of circular radial deflection as an instrument and its applications are described. In the electronic circuit of the instrument, the linearity of a deflected pulse on a circular sweep is especially contribed by employing a multiplying circuit, not to mention the one of a circular time base itself. A sequence of random pulses was recorded on a circular sweep of the CRT screen by means of one cycle unblanking due to a logic circuit. It seems that the intrument is suitable for measuring a decay curve of a short-lived nuclide and its pulse spectrum

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1005-1008
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• 2000

This paper presents a simple method to estimate short-circuit power dissipation and propagation delay for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. The macro model and its expressions estimating the delay of CMOS circuits, which is based on the current modeling expression, are also proposed after investigating the voltage waveforms at transistor output modes. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.1
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• pp.1-11
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• 1997

A BiCMOS circuit consists of the CMOS part which performs the logic function, and the bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential beavior. Also, stuck-on faults enhanced IDDQ (quiscent power supply current) at steady state. In this paper, a method is proposed which efficiently generates test patterns to detect stuck-open faults and stuck-on faults in BiCMOS circuits. The proposed method divides the BiCMOS circuit into pull-up part and pull-down part, and generates test patterns detect faults occured in each part by structural property of the BiCMOS circuit.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.1434-1444
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• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

• Journal of Korea Society of Industrial Information Systems
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• v.6 no.2
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• pp.74-79
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• 2001

The Stewing Motor has applied for engineering technology and that special used to auto mobile technology, robot technology and still more automatic machinery. If it make used to the motor for automatic machinery. That have high precision step of motor and high efficiency. n order to operation in this paper, the static position of motor to have analyzing, comparison of constant voltage control methode and constant current methode. And designed to a controller circuit of 4 phase unipolar driving and 2 phase bipolar driving of stepping motor.