• Journal of the Institute of Electronics Engineers of Korea SD
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• 제40권10호
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• pp.52-62
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• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제44권2호
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• pp.121-126
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• 2007

This paper describes a 9.09 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with Samsung $0.35{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the post layout simulation. The demultiplexer is achieved the maximum data rate of 9.09 Gb/s and the average power consumption of 69.93 mW. This circuit is expected to operate at higher speed than 9.09 Gb/s in the deep-submicron process of the high operating frequency.

• The Journal of the Korea institute of electronic communication sciences
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• 제7권6호
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• pp.1301-1308
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• 2012

In this paper, the low-power clock generator synchronized with the AC power signal using the adiabatic dynamic CMOS logic (ADCL) buffer is proposed for adiabatic logics. To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the ADCL, the clock signal of logic circuits should be synchronized with the AC power source. The clock signal for an adiabatic charging and discharging with the AC power signal was generated with the designed Schmitt trigger circuit and ADCL frequency divider using the ADCL buffer. From the simulation result, the power consumption of the proposed clock generator was estimated with approximately 1.181uW and 37.42uW at output 3kHz and 10MHz respectively.

• Journal of the Institute of Electronics and Information Engineers
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• 제54권1호
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• pp.41-45
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• 2017

This paper presents a method of constructing the efficiency multiple output switching function of the combinational logic systems. The proposed method reduce the optimized input variable pair and output variable pair after we obtained the final multiple output switching function which was time based multiplexing and obtained the common multiple end node extension logic decision diagram. Also the proposed method have an advantage of the cost, input-output node number, circuit simplification, increment of the arithmetic speed, and more regularity and extensibility compare with previous method.

• Journal of IKEEE
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• 제8권1호
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• pp.22-32
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• 2004

In this paper, we proposed MOVAG(Multi Output Value Array Graphs) based on OVAG by Honghai Jiang to construct multiple valued logic function The MDD(Muliple-valued Decision Diagra) needs many processing time and efforts in circuit design for given multi-variable function by D.M.Miller, and we designed a MOVAG which has reduce the data processing time and low complexity. We propose the construction algorithm and input matrix selection algorithm and we designed the multiple-valued logic circuit using T-gate and verified by simulation results.

• Journal of Sensor Science and Technology
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• 제29권1호
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제59권3호
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• pp.569-574
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• 2010

The full bridge converter have been used for high power system that is needed to switch the big current. So, EMI and stability problem is occurred. The Soft switching method is the solution to solve the above problem, But implementation of soft switching(ZVS: Zero Voltage Switching) is so complicate and expensive because of the DSP MCU and shift circuit. In this paper, we introduce the technical method for driving circuit of ZVS full bridge converter with 1st order delay circuit and logic elements. The realization of this method is so simple and cheap. The effectiveness of the proposed circuit is verified by experimental results.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 한국조명전기설비학회 2006년도 춘계학술대회 논문집
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• pp.407-409
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• 2006

This paper presents the methods of designing the control circuits for a Class D amplifier to have a peak performance. The proposed approach is based on the three functional components - a carrier generator, a feedback circuit and a dead-time circuit. First the analog signal is applied to the controller, which outputs the 3 level PWM waveform. The controller used for this experiment is made of the operational amplifier and the logic circuit. The experimental results show that the control circuit performs with satisfaction and its output is proportional to input audio signal, providing a satisfactory 3 level PWM pattern. From this design methodology, by implementing a proposed control circuit we can achieve the efficient Class D amplifier using the half-bridge, full-bridge or push-pull topology at the output stage.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• 제11B권4호
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• pp.185-192
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• 2001

In SRM drive, the ON·OFF angles of each phase switch should be accurately controlled in order to control the torque and speed stably. The accuracy of the switching angles is dependent upon the resolution of the encoder and the sampling period of the microprocessor, that are used to provide the information of the rotor position and to control the SRM power circuit, respectively. However, as the speed increases, the amount of the switching angle deviation from the preset values is also increased. Therefore, the low cost encoder suitable for the practical and stable SRM drive is proposed and the control algorithm to provide the switching signals using the simple digital logic circuit is also presented in this paper, As a result, a stable high speed SRM drive can be achieved by the high resolution switching angle control and it is verified from the experiments that the proposed encoder the logic controller can be a powerful candidate for the practical low cost SRM drive.

• Journal of the Korean Institute of Telematics and Electronics B
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• 제31B권1호
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• pp.57-63
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• 1994

The logic function synthesis using ULM U$_h$ is constructed based on canonic Reed-Muller expansion coefficient for a given function. This paper proposes the fast synthesis algorithm using ULM U$_h$ for ternary function. By using circuit cost and synthesis method of proposed in this paper, order of control input variable minimum number of ULM U$_h$ can be decided in the synthesis of n-variable ternary function. Accordingly, this method enables to optimum circuit realization for ternary function synthesis using ULM ULM U$_h$ and can be applied to ternary function synthesis using ULM U$_h$. The complexity of search for select the order of all control input variables is (n+2)(n-1)/2.