• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.353-356
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• 1999

A 3.3V PLL(Phase Locked loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage to frequency linearity of VCO(Voltage controlled oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30MHz~1㎓ with a good linearity. The DC-DC voltage up/down converter is utilized to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6${\mu}{\textrm}{m}$ n-well CMOS process. The simulation results show a locking time of 2.6$\mu$sec at 1Hz, Lock in range of 100MHz~1㎓, and a power dissipation of 112㎽.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.136-141
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• 2016

A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been proposed. In this paper, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and locking time of conventional PLL.

• Proceedings of the KSR Conference
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• 2007.11a
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• pp.1012-1017
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• 2007

To reduce the cost and the time of transport in Eurasian railroad networks such as TKR(Trans-Korea Railway), TCR(Trans-China Railway) and TSR(Trans-Siberia Railway) owing to the problem of different track gauges (narrow/standard/broad gauge), it is important to develop the gauge - adjustable wheelset system to adapt easily to these gauges. Moreover, this system accomplishes periodically a conversion operation from the gauge variable segment between different gauge. Gauge adjustable compression coil spring during conversion process accomplishes repetitively a central role for operation mechanism between flange and locking part. Therefore, to assure the safety of the gauge-adjustment wheelset system, it is necessary to stress analysis of the optimized spring in the system. In this study, it was performed to optimal design of the spring for stress analysis by using the genetic algorithm.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 1995.06a
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• pp.47-54
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• 1995

Rotary forging process has many advantages such as compacting of machine, low price of facilities and good quality of products. The last presented was a technical report about rotary forging press in the 100-ton class, which has the only orbital motion limited to the forming of axisymmetric parts. In this paper, the newly developed rotary forging press is introduced. The maximum capacity of forming load is 280 ton and five locking motion, this is, orbital, straight pivot, spiral and two kinds of clover can be available. This machine consists of transmission, double eccentric bush, rocking shaft, die set and hydraulic unit. Especially, the supports of rocking shaft and double eccentric bush are so crucial that hydrostatic bearings are adopted. Finally, it is expected that the technical know-how obtained in this research can be applied to the manufacturing of the another machine with large capacity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.520-527
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• 2016

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.697-699
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• 2017

A novel structure of phase locked loop (PLL) which has small size with D Flip-Flop and sub charge pump has been proposed. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.698-701
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• 2016

A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been proposed. In this paper, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and locking time of conventional PLL.

• Structural Engineering and Mechanics
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• v.12 no.6
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• pp.595-614
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• 2001

This paper studies the behaviour of a homogeneous cable in a horizontal rigid duct and loaded by an axial compressive force. This behaviour is characterized by spatial buckling modes, named sinusoidal and helical, due to friction and total or partial cable locking. The evaluation of critical buckling loads involved by drilling technology has been studied by many authors. This work presents a new formulation, taking the friction effects into account, for the transmission of the axial load during the postbuckling process. New analytical expressions of pitches in both buckling cases are also given. A life-sized bench is presented, which permits to study the laying of optical fiber cables by squeezing them into an underground duct. Finally, analytical solutions are compared with experimental tests and finite element simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.8A
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• pp.644-649
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• 2003

Novel 622Mb/s burst-mode clock and data recovery (CDR) circuits with muxed oscillators are realized for passive optical network (PON) application. The CDR circuits are implemented with 0.35$\mu\textrm{m}$ CMOS process technology. Lock is accomplished on the first data transition and data are sampled in the optimal point. The experimental results show that the proposed CDR circuits recover the incoming 400Mbps-680Mbps burst mode input data without error.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.75-82
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• 2010

This paper presents a wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer for a multi-band single chip CMOS RFIC transceivers. A wideband VCO utilizes a 6-bit switched capacitor array bank for 2340~3940 MHz frequency range. VCO frequency calibration circuit is designed for optimal capacitor bank code selection before phase locking process. It finishes the calibration process in $2{\mu}s$ over the whole frequency band. The LO generation block has selectable multiple division ratios of ${\div}2$, ${\div}16$, and ${\div}32$ to generate LO I/Q signals for T-DMB/DAB/FM Radio systems in L-Band (1173~1973 MHz), VHF-III (147~246 MHz), VFH-II (74~123 MHz), respectively. The measured integrated phase noise is quite low as it is lower than 0.8 degree RMS over the whole frequency band. Total locking time of the ${\Delta}{\Sigma}$ frequency synthesizer including VCO frequency calibration time is less than $50{\mu}s$. The wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer is fabricated in $0.13{\mu}m$ CMOS technology, and it consumes 15.8 mA from 1.2 V DC supply.