• The Transactions of the Korea Information Processing Society
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• v.6 no.9
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• pp.2442-2450
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• 1999

The audit logging system is to write the details of systems use and access on networks. These details are used for trailing the route, when illegal access or using system resource is occurred on networks. The logging system therefore, might be the first target of intruder. We developed the logging system which writes the information of logging and command execution on UNIX system. And we prepared the self-protecting functions of blocking intruder's attack on the logging system. They are protecting the logging process and the log file. To protect the logging process, we made it keep changing the process ID to avoid the intruder's attack. To protect the log file, we use hard link and mandatory file locking, so it can make it impossible to delete or change log file.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.819-825
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• 2016

In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of $58.2^{\circ}$ for wide loop and $49.4^{\circ}$ for narrow loop is designed for stable operation and the phase margin of $45^{\circ}$ is maintained during both loops work together. It has been designed with a 1.8V 0.18um complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.107-113
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• 2014

A VCO (Voltage Controlled Oscillator) and a divide-by-4 high speed frequency divider are implemented using 65nm CMOS technology for 60GHz wireless communication system. The mm-wave VCO was designed by NMOS cross-coupled LC type using current source. The architecture of the divide-by-4 high speed frequency divider is differential ILFD (Injection Locking Frequency Divider) with varactor to control frequency range. The frequency divider also uses current sources to get good phase noise characteristics. The measured results show that the VCO has 64.36~67.68GHz tuning range and the frequency divider divides the VCO output by 4 exactly. The high output power of 5.47~5.97dBm from the frequency divider is measured. The phase noise of the VCO including the frequency divider are -77.17dBc/Hz at 1MHz and -110.83dBc/Hz at 10MHz offset frequency. The power consumption including VCO is 38.4mW with 1.2V supply voltage.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 1995.04a
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• pp.17-27
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• 1995

For the post-buckling and elasto-plastic analysis of shell structures, the total Lagrangian formulation is presented based upon the degenerated shell element. Geometrically correct formulation is developed by updating the direction of normal vectors in the iteration process and evaluating the total Green-Lagrange stain corresponding U total displacements. In the calculation of the stiffness matrix, the element formulation takes into account the effect of finite rotation increments by retaining second order rotation terms in the incremental displacement field. The selective or reduced integration scheme using the heterosis element is applied in order to overcome both shear locking phenomena and the zero energy mode. The load/displacement incremental scheme is adopted for geometric non-linear F .E. analysis. Based on such methodology, the computer program is developed and numerical examples to demonstrate the accuracy and the effectiveness of the proposed shell element are presented and compared with references's results.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.6
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• pp.1133-1138
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• 2007

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.

• Journal of Welding and Joining
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• v.4 no.2
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• pp.47-52
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• 1986

Friction Welds are formed by the mechanisms of diffusion as well as mechanical inter-locking. The severe plastic flow at the interface by the forge action of the process brings the subsurface so close together that detection of any unbounded area becomes very difficult. No reliable method is available so fat to determine the weld quality nondestructively. The paper presents an attempt to determine weld strength quantitatively using the ultrasonic pulseecho method. The new approach calculates the coefficient of reflection based on measured amplitudes of the echoes. This coefficient provides a single quantitative measurement which involves both acoustic energy reflected at the welded interface as well as transmitted across the interface. As a result, it was known that the quantitative relationship between the coefficient and the weld strength (torsional strength) could be drawn.

• Transactions of the Korean Society of Automotive Engineers
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• v.22 no.1
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• pp.77-84
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• 2014

The worm gear is used in the motor drive system of automotive CVVL because of its compactness and self-locking ability. A ZK worm and an involute helical gear can be meshed in order to reduce production cost. However, the gearing is not suitable for the reliability and the NVH problem. To improve the dynamic performances, an optimal design process is considered. The transmission error is calculated theoretically and minimized with the several gear design parameters. An inequality condition such as the teeth interference elimination is added.

• Journal of Korean Neurosurgical Society
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• v.45 no.3
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• pp.182-184
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• 2009

Acute traumatic spondylolisthesis at L5-S1 level is a rare condition, almost exclusively the result of major trauma, frequently associated with transverse process fractures and severe neurologic deficits. Recently, open reduction and internal fixation with posterior stabilization has been the method of treatment most frequently reported. We report a rare case of traumatic L5-S1 spondylolisthesis with a unilateral facet locking with a review of literatures.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.275-278
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• 2008

In this paper, I propose the full CMOS FLL(frequency locked loop) circuit. The proposed FLL circuit has a simple structure which contains a FVC(frequency-to-voltage converter), an operational amplifier and a VCO(voltage controlled oscillator). The operation of FLL circuit is based on frequency comparison by the two FVC circuit blocks. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. The circuit is designed by 0.35${\mu}m$ process and simulation carried out with HSPICE. Simulation results are shown to illustrate the performance of the proposed FLL circuit.

• ETRI Journal
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• v.34 no.4
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• pp.518-526
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• 2012

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.