• 한국항해항만학회:학술대회논문집
• /
• 한국항해항만학회 2002년도 춘계학술대회논문집
• /
• pp.13-19
• /
• 2002

In inner harbour of Inchon Port, there are two lock gates (50KT, 10KT) which have two gates per lock gate in inner/outer sides except a gate in inner harbour side 7f 10KT. Due to the lack of the fore-mentioned gate, the use of 10KT lock gate Is suspended in every 3 years for regular maintenance. Now an additional gate is under construction in order to improve the efficiency of the 10KT lock gate. This paper will be aimed to evaluate the operational utilization levels of lock gates in present and future. The present operational utilization levels of lock gates are 0.2119 in 10KT lock gate, 0.2051 in 50KT lock gate which were considered the 46.5 closed days every 3 years for 10KT regular maintenance. The levels are estimated to 0.2246(10KT), 0.2539(50KT) in 2006 and 0.2241(10KT), 0.2560(50KT) in 2011. The levels of 50KT lock gate are evaluated to be more rapidly increased up to 24.5% in 2011.

• Journal of Korean Dental Science
• /
• 제4권2호
• /
• pp.85-91
• /
• 2011

Some treatment methods have been proposed for patients with chronic closed lock of temporomandibular joint. We report a conservative treatment for patients who had chronic closed lock of temporomandibular joint and who did not want surgical treatment. Two patients who had been treated in the Template clinic, Soonchunhyang University Bucheon Hospital, are the subjects of this report. The subjects had chronic closed lock symptom for over 3 months after an onset of locking; conventional therapies had no effect. The subjects were treated by making them wear a Template appliance while sleeping and exercise for 10 hours a day. After periodic follow-up, significant improvement was observed for Template treatment in terms of the maximal mouth opening range. When conventional therapy is expected to be ineffective, The Template appliance can be used as conservative treatment for temporomandibular disorders patients with chronic closed lock of temporomandibular joint.

• Tribology and Lubricants
• /
• 제20권4호
• /
• pp.183-189
• /
• 2004

The floating ring seal is used in an oxidizer and a fuel pump of the turbo pump unit in the liquid rocket engine to optimize a leakage without rubbing phenomenon. The damper floating ring seal, one of the floating ring seals, is with round hole pattern surfaces. It can reduce the leakage by increased friction factor that obtained from experimental data. In this paper, the leakage test about floating ring seal and damper floating ring seal was conducted. The test result showed the leakage performance of damper floating ring seal was better than the leakage performance of floating ring seal. With the leakage test the lock-up and rotation test about seal was conducted and that position is measured. The relatively large lock-up eccentric ratio was obtained from the test result of damping floating ring seal. The attitude angle of seal increases with increasing of shaft rotation.

• 한국소음진동공학회:학술대회논문집
• /
• 한국소음진동공학회 2004년도 춘계학술대회논문집
• /
• pp.820-825
• /
• 2004

The floating ring seal is used in an oxidizer and a fuel pump of the turbo pump unit in the liquid rocket engine to optimize a leakage without rubbing phenomenon. The damper floating ring seal, one of the floating ring seals, is with round hole pattern surfaces. It can reduce the leakage by increased friction factor that obtained from experimental data. In this paper, the leakage test about floating ring seal and damper floating ring seal was conducted. The test result showed the leakage performance of damper floating ring seal was better than the leakage performance of floating ring seal. With the leakage test the lock-up and rotation test about seal was conducted and that position is measured. The relatively large lock-up eccentric ratio was obtained from the test result of damping floating ring seal. The attitude angle of seal increases with increasing of shaft rotation

• 소성∙가공
• /
• 제17권2호
• /
• pp.124-129
• /
• 2008

Net shape forging technologies give many effects into the costs and qualities for the finished products. So, the studies to reduce the additional machining amount are very important in forging industry. Specially, there are two main topics in cold forging industry, such as, tool life and precision forging. In this study, new forging technique was proposed to eliminate the machining process for fixing up the length and improve the lead accuracy of gear. The luck-up hub is manufactured through many processes, such as upsetting, piercing and direct extrusion. The gear is formed in direct extrusion process; however, lead accuracy of the gear is over allowance limit. Therefore, the additional sizing process must be added. In this study, process design for closed-die forging of a lock-up hub used for a component of automobile transmission was made using three-dimensional finite element simulations, and the strain distributions and velocity distributions are investigated through the post processor. The rigid-plastic finite-element method for back pressure forging has been used in order to reduce development time and die cost. Using the FEM simulation, we found the optimum value of back pressure. The prototypes of lock-up hub parts were forged into the net-shape. In the experiment, lead precision of tooth are measured by the CCMM(Contact Coordinate Measuring Machine). The dimensional accuracy of forged part was improved up to the 40% when back press was applied.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제11권2호
• /
• pp.73-79
• /
• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.

• 대한기계학회논문집A
• /
• 제34권8호
• /
• pp.1129-1136
• /
• 2010

체결클러치에 부착된 댐퍼스프링은 유체커플링에서 직결로 변환될 때 발생하는 엔진 토크의 진동을 흡수하는 역할을 한다. 본 연구에서는 체결클러치의 성능을 좌우하는 압축스프링 및 지지 판 구조물의 최적설계를 통해서 새로운 설계형상을 제안하였다. 체결클러치와 연결된 엔진, 변속기, 구동축 및 휠, 차체질량 등 주요 부품들을 다 포함하는 다물체 동역학모델을 구성하여 공진 회피에 필요한 스프링상수를 계산하였다. 또한 어닐링 모사법에 의한 스프링 최적설계코드를 개발한 후 스프링상수, 최대충격토크, 수축각도, 스프링개수, 피로강도 등을 입력하여 압축 스프링의 사양을 최적화하였다. 이들 스프링을 지지하는 3 가지의 판에 대해서 컴플라이언스를 최소화하고 체적비를 0.3 이하로 하는 위상최적화를 수행하여 새로운 형상을 제안하였다.

• 한국항해항만학회지
• /
• 제26권2호
• /
• pp.177-182
• /
• 2002

인턴항의 내항에는 10K 덴 50K 갑문중 10KT 갑문의 내측문짝만이 1련만 설치되어 있는 관계로 매 3년마다 시행되는 문짝의 정기 수리 기간중 10KT 사용이 전면 중단되고 있으므로, 정부에서는 갑문운영의 효율성을 증대시키기 위하여 10KT 갑문의 내측문짝을 1련 증설하는 공사를 시행중에 있다. 본 논문에서는 이들 갑문의 현재 및 장래 운영 수준을 평가함을 목적으로 하였다. 연구결과, 갑문의 1998년도 운영 수준은 10KT는 0.2119, 50KT는 0.2061이며, 이는 10KT의 정기수리로 매3년 46.5일간 폐쇄를 고려한 것이다. 2006년의 운영수준은 0.2246(10KT), 0.2539(50KT)이며, 2011년은 0.2241(10KT), 0.2560(50KT)로 추정되었으며, 특히 50KT 갑문의 운영수준이 2011년도에 1998년도보다 24.5%가지 더욱 급격히 증가될 것으로 평가되었다.

• 조명전기설비학회논문지
• /
• 제20권9호
• /
• pp.70-77
• /
• 2006

We have fabricated an integrated three-phase flux-lock type SFCL, which consists of an YBCO($YB_a2Cu_3O_7$) thin film and a flux-lock reactor wound around an iron core of each phase. In order to apply the SFCL in a real power system, fault analyses for the three-phase system are essential. The short-circuit currents were effectively limited by adjusting the numbers of winding of each secondary coil and their winding directions. The flux flow generated in the iron core cancelled out under the normal operation due to the parallel connection between primary and secondary windings. However, the flux-lock type SFCL with same iron core was operated just after the fault due to the flux generating in the iron core. To analyze the current limiting characteristics, the additive polarity winding was compared with the subtractive one in the flux lock reactor. Whenever a single line-to-ground fault occurred in any phase, the peak value of the line current of the fault phase in the additive polarity winding increased up to about 12.87 times during the first-half cycle. On the other hand, the peak value in the subtractive polarity winding increased up to about 34.07 times under the same conditions. This is because the current flow between the primary and the secondary windings changed to additive or subtractive status according to the winding direction. We confirmed that the current limiting behavior in the additive polarity winding was more effective for a single-line-to-ground fault

• Journal of information and communication convergence engineering
• /
• 제10권2호
• /
• pp.187-193
• /
• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.