• 전자공학회논문지
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• 제51권2호
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• pp.46-52
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• 2014

본 논문은 다중 이득 제어를 통하여 빠른 lock-time을 갖는 디지털 위상 주파수 검출기 회로를 제안한다. 기준신호와 피드백 신호의 위상 차이가 클 때, 위상 차이가 적으면서 lock에 근접했을 때, lock 이후의 세 경우에 따라 디지털 위상 동기 루프의 이득을 다르게 설정하여 lock-time을 효과적으로 줄일 수 있다. 시뮬레이션 결과를 통해 제안된 기법을 적용함으로써 기존의 단일 이득 제어 구조보다 lock-time을 약 100배 개선시킬 수 있음을 확인하였다.

• Journal of electromagnetic engineering and science
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• 제11권2호
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• pp.105-112
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• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

• 전자공학회논문지B
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• 제30B권2호
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• pp.33-43
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• 1993

Lock mechanism is essential for synchronization on the multiprocessor systems. Lock mechanism needs to reduce the time for lock operation in low lock contention. Lock mechanism must consider the case of the high lock contention. The conventional lock control scheme in memory results in the increase of bus traffic and memory utilization in lock operation. This paper suggests a lock scheme which stores the lock data in cache and manages it efficiently to reduce the time spent in lock operation when the lock contention is low on a multiprocessor system built on HiPi-bus(Highly Pipelined bus). This paper also presents the design of the HIPi-CLOCK (Highly Pipelined bus Cache LOCK mechanism) which transfere the data from on cache to another when the lock contention is high. The designed simulator compares the conventional lock scheme which controls the lock in memory with the suggested HiPi-CLOCK scheme in terms of the RMW(Read-Modify-Write) operation time using simulated trace. It is shown that the suggested lock control scheme performance is over twice than that of the conventional method in low lock contention. When the lock contention is high, the performance of the suggested scheme increases as the number of the shared lock data increases.

• 한국IT서비스학회지
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• 제13권3호
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• pp.323-331
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• 2014

This research is based on real-time service model that uses lock screen of smart devices which is mostly exposed to device users. The potential for lock screen space is immense due to their exposing time for user. The effect can be maximized by offering useful information contents on lock screen. This service model offers real-time keyword with abridged sentence. They match real-time keyword with news by using text matching algorithm and extracts kernel sentence from news to provide short sentence to user. News from the lock screen to match real-time query sentence, and then only to the original core of the ability to move a user evaluation was conducted after adding. The report provided a key statement users feel the lack of original Not if you go to an average of 5.71%. Most algorithms allow only real-time zoom key sentence extracted keywords can accurately determine the reason for that was confirmed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.963-966
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• 2003

This paper proposes a new locking algorithm of the delay locked loop (DLL) which reduces the lock-acquisition time and eliminates false locking problem to enlarge the operating frequency range. The proposed DLL uses the modified phase frequency detector (MPFD) and the modified charge pump (MCP) to avoid the false locking problem. Adopting a new lock detector that measures delay between elects helps the fast lock-acquisition time greatly. The idea has been confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process.

• 한국융합학회논문지
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• 제9권7호
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• pp.9-16
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• 2018

본 연구의 목적은 악의적인 사용자가 내부 출입을 위해 물리적인 충격으로 Door-Lock을 파손하는 경우가 있다. Door-Lock 시스템에 설정되어 있는 아날로그 변위 값과 일치하면 관리자 스마트폰에 실시간으로 파손 정보를 전송함으로써 신체 및 재산을 보호한다. 연구방법은 Door-Lock이 물리적인 충격으로 파손될 경우 등록된 사용자들에게 실시간으로 파손 정보를 전송하는 시스템을 제안한다. 그리고 Door-Lock에서 감지한 충격 정보와 감도조절부의 데이터를 비교한다. 제안한 시스템의 웹 서버에서는 Door-Lock에서 전송한 충격 정보를 DB에 저장한 후 충격 정보가 DB에 저장된 충격 감지 전송 기준 값보다 크면 SMS 모듈로 관리자에게 실시간으로 전송해서 악의적인 사용자의 불법적인 출입 정보를 확인한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.79-82
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• 2000

This paper describes a delay locked loop with selective starting point for use in a high-frequency systems. SSRDLL (selective starting point RDLL) has been simulated in a 0.25$\mu\textrm{m}$ standard n-well CMOS process parameter to realize a fast lock-on time. This DLL is shown to be insensitive to variations in PVTL. The simulated lock time of the proposed SSRDLL is within 4 clock cycles at 333㎒ clock input.

• Current Optics and Photonics
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• 제7권6호
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• pp.683-691
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• 2023

A typical terahertz time-domain spectroscopy system requires large, expensive, and heavy hardware such as a lock-in amplifier and a function generator. In this study, we replaced the lock-in amplifier and the function generator with a single sound card built into a typical desktop computer to significantly reduce the system size, weight, and cost. The sound card serves two purposes: 1 kHz chopping signal generation and raw data acquisition. A unique software lock-in (Python coding program to eliminate noise from raw data) method was developed and successfully extracted THz time-domain signals with a signal-to-noise ratio of ~40,000 (the intensity ratio between the peak and average noise levels). The built-in sound card with the software lock-in method exhibited sufficiently good performance compared with the hardware-based method.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2002년도 학술대회지
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• pp.245-248
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• 2002

Vortex lock-on or resonance in the flow behind a circular cylinder is visualized by a time-resolved PIV when a single frequency oscillation is superimposed on the mean incident velocity. Measurements are made of the $K{\'{a}}rm{\'{a}}n$ vortices in the wake-transition regime at the Reynolds number 360. Basically, natural shedding state is observed to compare with lock-on state. Wake motion by the change of the shedding frequency of lock-on state is investigated. When lock-on occurs, the vortex shedding frequency is found to be half the oscillation frequency as expected from previous experiments. The physical flow phenomena of natural shedding and lock-on states are analyzed with physical parameters of recirculation and vortex formation region. Consequently, it is found that the change of wake bubble plays an important role in the flow at the lock-on state. Vortex formation region is also actively changed like recirculation region as the lock-on occurs. Therefore, it is deduced that the recirculation region is closely related with the vortex formation region.

• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.410-415
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• 2011

In this paper, we investigated the fault current limiting and the load voltage sag suppressing characteristics of the flux-lock type SFCL, designed with the additive polarity winding, according to the variations of turn number's ratio and the comparative analysis between the resistive type and the flux-lock type SFCLs were performed as well. From the analysis for the short-circuit tests, the flux-lock type SFCL designed with the larger turn number's ratio was shown to perform more effective fault current limiting and load voltage sag suppressing operations compared to the flux-lock type SFCL designed with the lower turn number's ratio through the fast quench occurrence of the high-$T_C$ superconducting (HTSC) element comprising the flux-lock type SFCL. In addition, the recovery time of the flux-lock type SFCL after the fault removed could be confirmed to be shorter in case of the flux-lock type SFCL designed with the lower turn number ratio.