• Title/Summary/Keyword: Lock time

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Concurrency Control and Recovery Methods for Multi-Dimensional Index Structures (다차원 색인구조를 위한 동시성제어 기법 및 회복기법)

  • Song, Seok-Il;Yoo, Jae-Soo
    • The KIPS Transactions:PartD
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    • v.10D no.2
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    • pp.195-210
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    • 2003
  • In this paper, we propose an enhanced concurrency control algorithm that maximizes the concurrency of multi-dimensional index structures. The factors that deteriorate the concurrency of index structures are node splits and minimum bounding region (MBR) updates in multi-dimensional index structures. The proposed concurrency control algorithm introduces PLC(Partial Lock Coupling) technique to avoid lock coupling during MBR updates. Also, a new MBR update method that allows searchers to access nodes where MBR updates are being performed is proposed. To reduce the performance degradation by node splits the proposed algorithm holds exclusive latches not during whole split time but only during physical node split time that occupies the small part of a whole split process. For performance evaluation, we implement the proposed concurrency control algorithm and one of the existing link technique-based algorithms on MIDAS-3 that is a storage system of a BADA-4 DBMS. We show through various experiments that our proposed algorithm outperforms the existing algorithm in terms of throughput and response time. Also, we propose a recovery protocol for our proposed concurrency control algorithm. The recovery protocol is designed to assure high concurrency and fast recovery.

Theoretical and experimental study on ultrahigh-speed clock recovery system with optical phase lock loop using TOAD (TOAD를 이용한 40 Gbit/s OPLL Clock Recovery 시스템에 대한 연구)

  • Ki, Ho-Jin;Jhon, Young-Min;Byun, Young-Tae;Woo, Deok-Ha
    • Korean Journal of Optics and Photonics
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    • v.16 no.1
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    • pp.21-26
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    • 2005
  • 10 GHz clock recovery from 40 Gbit/s optical time-division-multiplexed(OTDM) signal pulses was experimentally demonstrated using an optical phase lock loop based on a terahertz optical asymmetric demultiplexer(TOAD) with a local-reference-oscillator-free electronic feedback circuit. The 10 GHz clock was successfully extracted from 40 Gbit/s signals. The SNR of the time-extracted 10 GHz RF signal to the side components was larger than 40 dB. Also we performed numerical simulation about the extraction process of phase information in TOAD. The lock-in frequency range of the clock recovery is found to be 10 kHz.

Wide Range Analog Dual-Loop Delay-Locked Loop (광대역 아날로그 이중 루프 Delay-Locked Loop)

  • Lee, Seok-Ho;Kim, Sam-Dong;Hwang, In-Seok
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.44 no.1
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    • pp.74-84
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    • 2007
  • This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

Numerical analysis of the vortex induced vibration of the 2-D cylinder using dynamic deforming mesh (동적격자변형기법을 이용한 2차원 실린더의 와류유발진동에 대한 수치해석)

  • Lee, Namhun;Baek, Jiyoung;Lee, Seungsoo
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.41 no.1
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    • pp.1-9
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    • 2013
  • In this paper, numerical simulations are performed on the lock-in phenomena of vortex induced vibration(VIV) of a two dimensional cylinder. A deforming grid as well as a rigidly moving grid are used to simulate the movement of the cylinder. The grid deformation is accomplished by the linear spring analogy. Converged solutions, which are obtained by controling the grid size and the non-dimensional time step, are used for comparison and validation of the analysis results. Moreover, the efficiency and the accuracy of the coupling methods for fluid-structure interaction are examined.

GPS/INS Integration using Vector Delay Lock Loop Processing Technique

  • Kim, Hyun-Soo;Bu, Sung-Chun;Jee, Gyu-In
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.2641-2647
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    • 2003
  • Conventional DLLs estimate the delay times of satellite signals individually and feed back these measurements to the VCO independently. But VDLL estimates delay times and user position directly and then estimate the feedback term for VCO using the estimated position changes. In this process, input measurements are treated as vectors and these vectors are used for navigation. First advantage of VDLL is that noise is reduced in all of the tracking channels making them less likely to enter the nonlinear region and fall below threshold. Second is that VDLL can operate successfully when the conventional independent parallel DLL approach fails completely. It means that VDLL receiver can get enough total signal power to track successfully to obtain accurate position estimates under the same conditions where the signal strength from each individual satellite is so low or week that none of the individual scalar DLL can remain in lock when operating independently. To operate VDLL successfully, it needs to know the initial user dynamics and position and prevents total system from the divergence. The suggested integration method is to use the inertial navigation system to provide initial dynamics for VDLL and to maintain total system stable. We designed the GPS/INS integrated navigation system. This new type of integrated system contained the vector pseudorange format generation block, VDLL signal processing block, position estimation block and the conversion block from position change to delay time feedback term aided by INS.

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Immersed Boundary Method for Flow Induced by Transverse Oscillation of a Circular Cylinder in a Free-Stream (가상경계법을 사용한 횡단 진동하는 실린더 주위의 유동 해석)

  • Kim, Jeong-Hu;Yoon, Hyun-Sik;Tuan H.A.;Chun, Ho-Hwan
    • Journal of the Society of Naval Architects of Korea
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    • v.43 no.3 s.147
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    • pp.322-330
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    • 2006
  • Numerical calculations are carried out for flow past a circular cylinder forced oscillating normal to the free-stream flow at a fixed Reynolds number equal to 185. The cylinder oscillation frequency ranged from 0.8 to 1.2 of the natural vortex-shedding frequency, and the oscillation amplitude extended up to 20% of the cylinder diameter. IBM (Immersed Boundary Method) with direct momentum forcing was adopted to handle both of a stationary and an oscillating cylinder Present results such as time histories of drag and lift coefficients for both stationary and oscillating cases are in good agreement with previous numerical and experimental results. The instantaneous wake patterns of oscillating cylinder with different oscillating frequency ratios showed the synchronized wakes pattern in the lock-in region and vortex switching phenomenon at higher frequency ratio than the critical frequency ratio.

Lock-in and drag amplification effects in slender line-like structures through CFD

  • Belver, Ali Vasallo;Iban, Antolin Lorenzana;Rossi, Riccardo
    • Wind and Structures
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    • v.15 no.3
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    • pp.189-208
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    • 2012
  • Lock-in and drag amplification phenomena are studied for a flexible cantilever using a simplified fluid-structure interaction approach. Instead of solving the 3D domain, a simplified setup is devised, in which 2D flow problems are solved on a number of planes parallel to the wind direction and transversal to the structure. On such planes, the incompressible Navier-Stokes equations are solved to estimate the fluid action at different positions of the line-like structure. The fluid flow on each plane is coupled with the structural deformation at the corresponding position, affecting the dynamic behaviour of the system. An Arbitrary Lagrangian-Eulerian (ALE) approach is used to take in account the deformation of the domain, and a fractional-step scheme is used to solve the fluid field. The stabilization of incompressibility and convection is achieved through orthogonal quasi-static subscales, an approach that is believed to provide a first step towards turbulence modelling. In order to model the structural problem, a special one-dimensional element for thin walled cross-section beam is implemented. The standard second-order Bossak method is used for the time integration of the structural problem.

Improving Safety of Biycle Driver System using Arduino (아두이노를 활용한 자전거 운전자 안전 향상 시스템)

  • Bae, Tae-Hyeon;Kang, Jong-Ho;Park, Ji-Won;Kim, Bum-Su;Lee, Boong-Joo
    • The Journal of the Korea institute of electronic communication sciences
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    • v.12 no.4
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    • pp.525-532
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    • 2017
  • The system is consisted of arduino and sensors for protecting bicycle and safety of driver. The speed indicator is composed of speed alarms which are less than 15km/h, 15~30km/h, over 30km/h through limit switch. At that time, the accuracy is 96.6% compared to actual speed. Also, It gives a person warning ablut the obstacle of 5cm tall through ultrasonic sensor in night. Auto Lock System is operated to protect bicycle and the text message is sent to the user, if the bicycle lock was broken. This system puts emphasis on safety and usability, providing a application to know consuming calories.

Current Limiting Characteristics of a SFCL with Two Triggered Current Limiting Levels in a Simulated Power Distribution System (모의배전계통에 두 트리거 전류레벨을 이용한 초전도한류기의 전류제한 특성 분석)

  • Ko, Seok-Cheol;Han, Tae-Hee
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.2
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    • pp.134-139
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    • 2013
  • When the accident occurred in power distribution system, it needs to control efficiently the fault current according to the fault angle and location. The flux-lock type superconducting fault current limiters (SFCL) can quickly limit when the short circuit accidents occurred and be made the resistance after the fault current. The flux-lock type SFCL has a single triggering element, detects and limits the fault current at the same time regardless of the size of the fault current. However, it has a disadvantage that broken the superconductor element. If the flux-lock type SFCL has separated structure of the triggering element and the limiting element, when large fault current occurs, it can reduce the burden of power and control fault current to adjust impedance. In this paper, this system is composed by triggering element and limiting element to analyze operation of limiting current. When the fault current occurs, we analyzed the limiting and operating current characteristics of the two triggering current level, and the compensation characteristics of bus-voltage sag according to the fault angle and location.

Voltage-Current Characteristics According to Fault Period of Flux-Lock SFCL with subtractive polarity winding (감극결선용 자속구속형 전류제한기의 사고주기별 전압전류 특성)

  • Han, Tae-Hee;Hwang, Jong-Sun;Cho, Yong-Sun;Park, Hyoung-Min;Nam, Guong-Hyun;Lee, Na-Young;Choi, Hyo-Sang;Lim, Sung-Hun;Chung, Dong-Chul;Choi, Myoung-Ho
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.12a
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    • pp.101-102
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    • 2006
  • We investigated the characteristics of flux-lock type superconducting fault current limiter (SFCL) by the fault cycles. Since the recovery characteristics of a superconducting element in the flux-lock type SFCL were dependent on the winding' direction between two coils, the analysis for the recovery characteristics of this type SFCL together with the current limiting characteristic is necessary to apply it to power system. As the fault cycles was increased from 1 cycle to 5 cycles, the initial limiting current ($I_{ini}$) and quench characteristic were mostly same. As the fault period increases, the recovery time of the superconducting element increases. The consumed energy and recovery characteristics in a superconducting element show the same tendency.

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