• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.2
• /
• pp.46-52
• /
• 2014

This paper presents a multiple gain controlled digital phase and frequency detector with a fast lock-time. Lock-time of the digital PLL can be significantly reduced by applying proposed adaptive gain control technique. A loop gain of the proposed digital PLL is controlled by three conditions that are very large phase difference between reference and feedback signal, small phase difference and before lock-state, and after lock-state. The simulation result shows that lock-time of the proposed multiple gain controlled digital PLL is 100 times faster than that of the conventional structure with unit gain mode.

• Journal of electromagnetic engineering and science
• /
• v.11 no.2
• /
• pp.105-112
• /
• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.30B no.2
• /
• pp.33-43
• /
• 1993

Lock mechanism is essential for synchronization on the multiprocessor systems. Lock mechanism needs to reduce the time for lock operation in low lock contention. Lock mechanism must consider the case of the high lock contention. The conventional lock control scheme in memory results in the increase of bus traffic and memory utilization in lock operation. This paper suggests a lock scheme which stores the lock data in cache and manages it efficiently to reduce the time spent in lock operation when the lock contention is low on a multiprocessor system built on HiPi-bus(Highly Pipelined bus). This paper also presents the design of the HIPi-CLOCK (Highly Pipelined bus Cache LOCK mechanism) which transfere the data from on cache to another when the lock contention is high. The designed simulator compares the conventional lock scheme which controls the lock in memory with the suggested HiPi-CLOCK scheme in terms of the RMW(Read-Modify-Write) operation time using simulated trace. It is shown that the suggested lock control scheme performance is over twice than that of the conventional method in low lock contention. When the lock contention is high, the performance of the suggested scheme increases as the number of the shared lock data increases.

• Journal of Information Technology Services
• /
• v.13 no.3
• /
• pp.323-331
• /
• 2014

This research is based on real-time service model that uses lock screen of smart devices which is mostly exposed to device users. The potential for lock screen space is immense due to their exposing time for user. The effect can be maximized by offering useful information contents on lock screen. This service model offers real-time keyword with abridged sentence. They match real-time keyword with news by using text matching algorithm and extracts kernel sentence from news to provide short sentence to user. News from the lock screen to match real-time query sentence, and then only to the original core of the ability to move a user evaluation was conducted after adding. The report provided a key statement users feel the lack of original Not if you go to an average of 5.71%. Most algorithms allow only real-time zoom key sentence extracted keywords can accurately determine the reason for that was confirmed.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.963-966
• /
• 2003

This paper proposes a new locking algorithm of the delay locked loop (DLL) which reduces the lock-acquisition time and eliminates false locking problem to enlarge the operating frequency range. The proposed DLL uses the modified phase frequency detector (MPFD) and the modified charge pump (MCP) to avoid the false locking problem. Adopting a new lock detector that measures delay between elects helps the fast lock-acquisition time greatly. The idea has been confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process.

• Journal of the Korea Convergence Society
• /
• v.9 no.7
• /
• pp.9-16
• /
• 2018

The purpose of this study is to prevent the malicious user from breaking the door-lock due to physical impact. If it matches the analog displacement value set in the door-lock system, it protects the body and property by transmitting damage information in real time to the manager smart phone. The research suggests a system that transmits damage information in real time to registered users when door-lock is damaged by physical impact. Then compare the impact information sensed by the door lock with the data of the sensitivity control unit. In the web server of the proposed system, after impact information transmitted from Door-Lock is stored in the DB, if the impact information is larger than the shock detection transmission reference value stored in the DB, it is transmitted to the administrator in real time by SMS module so that illegal access information.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.79-82
• /
• 2000

This paper describes a delay locked loop with selective starting point for use in a high-frequency systems. SSRDLL (selective starting point RDLL) has been simulated in a 0.25$\mu\textrm{m}$ standard n-well CMOS process parameter to realize a fast lock-on time. This DLL is shown to be insensitive to variations in PVTL. The simulated lock time of the proposed SSRDLL is within 4 clock cycles at 333㎒ clock input.

• Current Optics and Photonics
• /
• v.7 no.6
• /
• pp.683-691
• /
• 2023

A typical terahertz time-domain spectroscopy system requires large, expensive, and heavy hardware such as a lock-in amplifier and a function generator. In this study, we replaced the lock-in amplifier and the function generator with a single sound card built into a typical desktop computer to significantly reduce the system size, weight, and cost. The sound card serves two purposes: 1 kHz chopping signal generation and raw data acquisition. A unique software lock-in (Python coding program to eliminate noise from raw data) method was developed and successfully extracted THz time-domain signals with a signal-to-noise ratio of ~40,000 (the intensity ratio between the peak and average noise levels). The built-in sound card with the software lock-in method exhibited sufficiently good performance compared with the hardware-based method.

• Proceedings of the KSME Conference
• /
• 2002.08a
• /
• pp.245-248
• /
• 2002

Vortex lock-on or resonance in the flow behind a circular cylinder is visualized by a time-resolved PIV when a single frequency oscillation is superimposed on the mean incident velocity. Measurements are made of the $K{\'{a}}rm{\'{a}}n$ vortices in the wake-transition regime at the Reynolds number 360. Basically, natural shedding state is observed to compare with lock-on state. Wake motion by the change of the shedding frequency of lock-on state is investigated. When lock-on occurs, the vortex shedding frequency is found to be half the oscillation frequency as expected from previous experiments. The physical flow phenomena of natural shedding and lock-on states are analyzed with physical parameters of recirculation and vortex formation region. Consequently, it is found that the change of wake bubble plays an important role in the flow at the lock-on state. Vortex formation region is also actively changed like recirculation region as the lock-on occurs. Therefore, it is deduced that the recirculation region is closely related with the vortex formation region.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.24 no.5
• /
• pp.410-415
• /
• 2011

In this paper, we investigated the fault current limiting and the load voltage sag suppressing characteristics of the flux-lock type SFCL, designed with the additive polarity winding, according to the variations of turn number's ratio and the comparative analysis between the resistive type and the flux-lock type SFCLs were performed as well. From the analysis for the short-circuit tests, the flux-lock type SFCL designed with the larger turn number's ratio was shown to perform more effective fault current limiting and load voltage sag suppressing operations compared to the flux-lock type SFCL designed with the lower turn number's ratio through the fast quench occurrence of the high-$T_C$ superconducting (HTSC) element comprising the flux-lock type SFCL. In addition, the recovery time of the flux-lock type SFCL after the fault removed could be confirmed to be shorter in case of the flux-lock type SFCL designed with the lower turn number ratio.