• 전력전자학회논문지
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• 제2권2호
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• pp.29-34
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• 1997

본 논문에서는 단상 PWM 컨버터의 입력전류 제어계와 출력전압 제어계의 안정한 PI 이득을 설계하고 DSP를 이용하여 순시 제어기를 구현한다. DC link 전압 제어기는 연속영역에서 설계하여도 무방하나 입력전류 제어계는 이산화 영향을 무시할 수 없으므로 입력전류 제어계를 연산 시간을 고려하여 이산 영역에서 전달 함수를 구하여 설계한다. 또한 리플전압 추정 루틴을 통하여 실제 커패시터의 정전용량을 알아내는 알고리듬을 제시하고 이 알고리듬에 의하여 DC link 정전 용량을 과도상태에서도 추정해 낼수 있음을 보인다. 실험에 의하여 입력역률 99%와 부하급변시 전압 변동률 $\pm$5% 이하의 결과를 얻었다.

• 한국신뢰성학회지:신뢰성응용연구
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• 제12권2호
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• pp.67-78
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• 2012

An electric double-layer capacitor(EDLC) is an electrochemical capacitor with relatively high energy density, typically hundreds of times greater than conventional electrolytic capacitors. EDLCs are widely used for energy storage rather than as general-purpose circuit components. They have a variety of commercial applications, notably in energy smoothing and momentary-load devices, and energy-storage and kinetic energy recovery system devices used in vehicles, etc. This paper presents an accelerated degradation test of an EDLC with rated voltage 2.7V, capacitance 100F, and usage temperature $-40^{\circ}C{\sim}65^{\circ}C$. The EDLCs are tested at $50^{\circ}C$, $60^{\circ}C$, and $70^{\circ}C$, respectively for 1,750hours, and their capacitances are measured at predetermined times by constant current discharge method. The failure times are predicted from their capacitance deterioration patterns, where the failure is defined as 30% capacitance decrease from the initial one. It is assumed that the lifetime distribution of EDLC follows Weibull and Arrhenius life-stress relationship holds. The life-stress relationship, acceleration factor, and $B_{10}$ life at design condition are estimated by analyzing the accelerated life test data.

• Journal of Power Electronics
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• 제18권1호
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• pp.116-128
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• 2018

Conventionally, in order to reduce the ac components of the dc-link capacitors of the two-level Half-Bridge Voltage Source Inverter (HB-VSI), high dc-link capacitances are required. This necessitates the employment of short-lifetime and bulky electrolytic capacitors. In this paper, an analysis for the performance of low dc-link capacitances-based HB-VSI is presented to elucidate its ability to generate an enhanced fundamental output voltage magnitude without increasing the voltage rating of the involved switches. This feature is constrained by the load displacement factor. The introduced enhancement is due to the ac components of the capacitors' voltages. The presented approach can be employed for multi-phase systems through using multi single-phase HB-VSI(s). Mathematical analysis of the proposed approach is presented in this paper. To ensure a successful operation of the proposed approach, a closed loop current controller is examined. An expression for the critical dc-link capacitance, which is the lowest dc-link capacitance that can be employed for unipolar capacitors' voltages, is derived. Finally, simulation and experimental results are presented to validate the proposed claims.

• 한국전자파학회논문지
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• 제10권5호
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• pp.663-671
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• 1999

본 연구에서는 GaAs MESFET의 게이트-소오스 캐패시턴스($C_{gs}$)와 드레인-소오스 전류($I_{ds}$)의 비션형성에 의한 이득감소(Gain Compression) 및 위상왜곡(Phase Distortion)특성을 알아보고, 이를 최소화 할 수 있 는 소오스 및 부하 임피던스의 조건에 대해 조사하였다. 먼저 Volterra - Series 분석을 통하여, $C_{gs}(V_{gs})$와 $I_{ds}(V_{gs})$의 비선형특성을 조사하고, 각각의 비선형성분이 상호 소멸되는 소오스 및 부하 임피던스의 조건에서, 전체소자의 비선형성이 최소화 됨을 얄아보았다. 그리고 소오스 및 부하측정(Source, Load Pull)을 통하여 출 력전력값에 따라 최적의 선형성이 나오는 입출력 임피던스값을 찾고, Volterra-Series에서 구한 이론적인 결과와 비교 및 분석을 행하였다.

• 한국윤활학회:학술대회논문집
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• 한국윤활학회 2002년도 proceedings of the second asia international conference on tribology
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• pp.53-54
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• 2002

New lubrication mechanism for nanomachine is proposed. This mechanism utilizes the effect of diffusive double layer observed in hydrophobic colloidal solution. Basic idea of the theory is inspired by the research for possible mechanism of bacterial flagellar motor In this study, formulation of this mechanism is achieved and numerical calculation is performed. It is shown that this mechanism can produce enough load capacitance. Furthermore not only capacitance to sustain driving force of flagellar motor

• 전력전자학회:학술대회논문집
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• 전력전자학회 1997년도 전력전자학술대회 논문집
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• pp.27-33
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• 1997

In this paper, instantaneous controller of a single-phase PWM converter is realized using DSP. The stable PI gain of the input current and the DC link voltage control system is designed. The DC link voltage control system can be designed in continuous-time domain. But as for the input current control system, the descretizing effect cannot be ignored so it must be designed in descrete-time domain considering the calculation time. The capacitance estimating algorithm which can be acquired through the ripple voltage is proposed. By this algorithm the DC link capacitance can be estimated even under the transient state. Experimental results show the input power factor of 99.1% and the voltage variation rate of $\pm$5% according to the load variation.

• 한국정보기술응용학회:학술대회논문집
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• 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
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• pp.99-102
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• 2005

In the paper, a proposed VCO based on bondwire inductances and nMOS varactors was implemented in a standard $0.25\;{\mu}m$ CMOS process. Using the new drain current model and a propagation delay time model equations, the operation speed of CMOS gate will predict the dependence on the load capacitance and the depth of oxide, threshold voltage, the supply voltage, the channel length. This paper describes the result of simulation which calculated a gate propagation delay time by using new drain current model and a propagation delay time model. At the result, When the reverse bias voltage on the substrate changes from 0 voltage to 3 voltage, the propagation delay time is appeared the delay from 0.8 nsec to 1 nsec. When the reverse voltage is biased on the substrate, for reducing the speed delay time, a supply voltage has to reduce. The $g_m$ value of MOSFET is calculated by using new drain current model.

• ETRI Journal
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• 제33권1호
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• pp.6-12
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• 2011

A case study of an active transmitting patch antenna revealed a characteristic loop locus of DC power versus RF output power as drive frequency was varied, with an operational bandwidth substantially smaller than the impedance bandwidth of the radiator. An approximate simulation technique, based on separation of the output capacitance of the power transistor, yielded easily visualized plots of power dependence on internal load impedance, and a simple interpretation of the experimental results in terms of a near-resonance condition between the output capacitance and output packaging inductance.

• Journal of Information Display
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• 제2권4호
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• pp.63-67
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• 2001

The switching power loss due to the panel capacitance during sustain period in AC PDP driving system can be minimized by using the energy recovery circuits. We proposed a new energy recovery circuit, SER1 (Seoul national univ. Energy Recovery circuit 1st). The experimental results of its application to a 42-inch surface discharge type AC PDP showed superior performance of SER1 in energy recovery efficiency and low distortion voltage waveform. Energy recovery efficiency of SER1 was measured up to 92.3 %, and the power dissipation during the sustain period was reduced by 15.2 W in 2000 pulse/frame compared with serial LC resonance energy recovery circuit.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.1005-1008
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• 2000

This paper presents a simple method to estimate short-circuit power dissipation and propagation delay for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. The macro model and its expressions estimating the delay of CMOS circuits, which is based on the current modeling expression, are also proposed after investigating the voltage waveforms at transistor output modes. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.