• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.2 s.93
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• pp.149-153
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• 2005

A new method of power amplifier's linearity improvement using a Compact Microstrip Resonant Cell(CMRC) is proposed. It is found out that a CMRC at the input side gives better performance than that at the output. Tuning lines are used in the input and the output matching network to get the optimum performance. As a result, the 14.77 dB improvement fur the third-order IMD is obtained. And the size of the CMRC is only $17.1\times5.22mm$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.3 no.1
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• pp.63-69
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• 2010

In this paper, a new design method of asymmetrical configuration of main amplifier and peaking amplifier using changed bias point is proposed for excellent linearity, instead of the conventional Doherty structure. We have utilized the uneven wilkinson power divider for the unequal power drive at the input network of amplifiers. And we proposed a compensating method of the decreasing efficiency due to improving linearity using 3-stage Doherty structures. From the simulation results of asymmetrical Dohertry power amplifier and asymmetrical 3-stage Doherty power amplifier with uneven power drive are implemented. From the implementation and measurement results of the each amplifier, IMD characteristics have -55 dBc as the good efficiency of 13% compensates the decreased entire efficiency due to the improving linearity characteristics.

• Nuclear Engineering and Technology
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• v.55 no.2
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• pp.484-492
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• 2023

Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale + FPGA; meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the 'HU method' (HU TDC) and with 'both HU and MCT methods' (HU-MCT TDC) were measured and compared to those of the TDC with 'DDL alone' (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2002.11a
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• pp.377.2-377
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• 2002

In optical disk drives (ODD), the demands of high data density and high speed have been increasing rapidly to achieve high data capacity and data transfer rate The use of short wavelength laser and high track following performance are needed to raise data density and data rate. For high-performance actuator, the improvement of linearity and acceleration become more important. (omitted)

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.239-247
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• 1996

The accuracy of sample-and-hold amplifiers (SHA's) empolying a CMOS process in limited by nonideal factors such as linearity errors of an op amp and feedthrough errors of switches. In this work, after some linearity improvement techniques for an op amp are discussed, three different SHA's for video signal processing are designed, simulated, and compared. The CMOS SHA design techniques with a 12-bit level accuracy are proposed by minimizing cirucit errors based on the simulated results.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.547-548
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• 2008

Linearity improvement technique of transconductor is presented in the paper. In order to certify the linearity improvement of proposed transconductor, the 3rd-order Elliptic low-pass Gm-C filter which provides 5MHz cutoff is implemented by using the transconductor. According to the IIP3 measurement result of filters, proposed filter has higher IIP3 than normal source-degeneration filter; the In-band IIP3 of proposed and normal filter are 10.1 dBm and 7.5 dBm respectively. The filter is fabricated in 1P6M $0.18-{\mu}m$ CMOS while consuming the 3.3mW with 1.8 Vdd. The in-band input-referred noise voltage is $62.3{\mu}Vrms$ and the SFDR is 54.1 dB.

• Journal of Sensor Science and Technology
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• v.23 no.6
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• pp.392-396
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• 2014

The 2-dimensional silicon vertical Hall devices, which are sensitive to X,Y components of the magnetic field parallel to the surface of the chip, are fabricated using a modified bipolar process. It consists of the thin p-layer at Si-$SiO_2$ interface and n-epi layer to improve the sensitivity and influence of interface effect. Experimental samples are a sensor type K with and type J without $p^+$ isolation dam adjacent to the center current electrode. The results for both type show a more high sensitivity than the former's 2-dimensional vertical Hall devices and a good linearity. The measured non-linearity is about 0.8%. The sensitivity of type J and type K are about 66 V/AT and 200 V/AT, respectively. This sensor's behavior can be explained by the similar J-FET model.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.8
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• pp.500-508
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• 2004

This paper presents a new sensorless vector control system for high performance induction motor drives fed by a matrix converter with non-linearity compensation and disturbance observer. The nonlinear voltage distortion that is caused by commutation delay and on-state voltage drop in switching device is corrected by a new matrix converter modeling. The lumped disturbances such as parameter variation and load disturbance of the system are estimated by the radial basis function network (RBFN). An adaptive observer is also employed to bring better responses at the low speed operation. Experimental results are shown to illustrate the performance of the proposed system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.262-267
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• 2005

During several method of improvement efficient, We analyzed Doherty Amplifier That used by simple circuit and 180w PEP LDMOS to analyze improvement of efficient and linearity. We for testing performance of Doherty Amplifier compared with Balanced Class AB, the experimental results show when Peaking Amp $V_gs.P$=1.53V, the efficiency is increased at Maximum 11.6$\%$. After finding optimum bias point of linearity improvement by manual tuning gate bias, when WCDMA 4FA $V_gs.P$=3.68V IMSR could be increased maximum 3.34dB. especially, when we match bias point of Peaking amp at 1.53V, we could get a excellent efficiency increase and have fUR under -3203c at output power 43dBm.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.8-15
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• 2003

In this paper, the issue of the differential ring oscillator in designing low phase noise is linearity improvement of delay cell's load resistor. A novel differential delay cell that improves on the Maneatis load is proposed. The linearity improvement of load resistor results in lower phase noise in ring oscillator. For comparison of the phase noise characteristics, Ali Hajimiri's phase noise model is used. In order to have a low ISF(impulse sensitivity function), it is important to have a symmetry between rise time and fall time of oscillation waveform. The ISF value of ing oscillator based on the proposed delay cell is lower than that of the existing ring oscillators. Due to this result, the phase noise is improved by 2~3dBc/Hz for the same power dissipation and oscillation frequency.