• Title/Summary/Keyword: Line harmonic

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Input Current Harmonic Reduction of Inverer TIG Welder (인버터 TIG용접기의 전원전류 고조파 저감)

  • 김준호
    • Proceedings of the KIPE Conference
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    • 2000.07a
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    • pp.560-563
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    • 2000
  • In this paper we proposed AC/DC boost converter to improve input current harmonic reduction in TIG welder. The proposed harmonic reduction circuit with UC2854AN acting on constant switching frequency average current control has a three-loop control structure : the inner current loop the line voltage feed-forward loop and th outer voltage loop. Also we applied the constant current strategy on full bridge IGBT inverter to stabilized the output current using the analog PI controller. To demonstrate the practical significance of the proposed methods some simulation studies and experimental results are presented.

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Harmonic Analysis of TCSC Power Transmission System considering Load Characteristics (부하 특성을 고려한 TCSC 전력송전 시스템의 고조파 해석)

  • 정교범
    • Proceedings of the KIPE Conference
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    • 2000.07a
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    • pp.468-471
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    • 2000
  • This paper investigates the harmonics of TCSC power transmission system having nonlinear VI characteristic loads. Nonlinear VI characteristic components are modelled with Nortons harmonic current sources. The system parameters such as line impedances admittances and node voltages and the thyristor switching action are described in complex Fourier series. EMTP simulation studies with a detailed three-phase TCSC power transmission system are also performed in order to verify the harmonic analysis at the steady state.

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The comparison of harmonic detection methods on the Power line (상용(220V/60Hz)전원의 고조파 검출 방식의 비교)

  • Jung Dong-Youl;Hwang Hwan-Young;Park Chong-Yeun
    • Proceedings of the KIPE Conference
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    • 2004.07b
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    • pp.883-886
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    • 2004
  • The current harmonic detector consists of the load current detector and the notch filter. It obtains the harmonic current from the output of the load current detector using the Notch filter. The GIC in the notch filter is used instead of inductor to minimize the magnitude and phase characteristics variation caused by using twin-T notch filter and passive elements(inductor).

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A Study on the NGR problem for harmonic in Distribution system (배전계통의 고조파에 의한 NGR의 문제점에 관한 연구)

  • Park Hee Chul;Cho Nam Hun;Kang Moon Ho;Wang Young peel
    • Proceedings of the KIEE Conference
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    • summer
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    • pp.480-482
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    • 2004
  • This paper presents a study on the NGR problem for harmonic in distribution systems. Overheating of NGR (Neutral Ground reactor), by neutral current in distribution system, is important cause of transformer breakdown of substation. Countermeasures about zero-sequence component harmonic in neutral line are required.

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Desk-Top Robot with Power Factor Correction (역률개선 회로를 적용한 Desk-Top Robot)

  • Chun, Kwang-Su;Kim, Hak-Jin
    • Proceedings of the KIPE Conference
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    • 2007.07a
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    • pp.343-346
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    • 2007
  • Recently, many nations have released standard such as EN61000-3-2 to impose a limit on the harmonic current to prevent distortion of AC line and to save energy. Also, the limit on the harmonic current makes use of a trade barrier. Therefore, Power factor correction must have been suitable for a limit on the harmonic current. This paper presents AC servo motor drive to have merits of high power factor for Desk-Top Robot.

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A 125 MHz CMOS Delay-Locked Loop with 64-phase Output Clock (64-위상 출력 클럭을 가지는 125 MHz CMOS 지연 고정 루프)

  • Lee, Pil-Ho;Jang, Young-Chan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.259-262
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    • 2012
  • This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.

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Electrical Characteristic Changes of ZnO Varistors by Energy Absorption

  • Kim, Woo-Hyun;Hwang, Seong-Cheol;Wang, Guoming;Kil, Gyung-Suk;Ahn, Chang-Hwan
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.30 no.12
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    • pp.817-821
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    • 2017
  • As a ZnO varistor is subjected to electrical and environmental stresses, it degrades gradually, which may result in power interruption by short circuit. This study investigates changes in the electrical characteristics of ZnO varistors due to deterioration owing to energy absorption, and determines the optimal parameters for on-line diagnosis of the varistor. Two types of varistors were used for an accelerated aging experiment involving the application of the $8/20{\mu}s$ standard lightning impulse current. The electrical characteristics in terms of the reference voltage, total leakage current, resistive leakage current, and third-harmonic component of the total leakage current were measured, and their change rates were analyzed. The results revealed that the total leakage current increased slightly with an increase in the varistor absorbed energy, while the resistive leakage current and the third-harmonic component increased apparently. Therefore, the third-harmonic component of the total leakage current was proposed as the optimal parameter for on-line monitoring of ZnO varistor conditions.

Virtual Flux and Positive-Sequence Power Based Control of Grid-Interfaced Converters Against Unbalanced and Distorted Grid Conditions

  • Tao, Yukun;Tang, Wenhu
    • Journal of Electrical Engineering and Technology
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    • v.13 no.3
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    • pp.1265-1274
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    • 2018
  • This paper proposes a virtual flux (VF) and positive-sequence power based control strategy to improve the performance of grid-interfaced three-phase voltage source converters against unbalanced and distorted grid conditions. By using a second-order generalized integrator (SOGI) based VF observer, the proposed strategy achieves an AC voltage sensorless and grid frequency adaptive control. Aiming to realize a balanced sinusoidal line current operation, the fundamental positive-sequence component based instantaneous power is utilized as the control variable. Moreover, the fundamental negative-sequence VF feedforward and the harmonic attenuation ability of a sequence component generator are employed to further enhance the unbalance regulation ability and the harmonic tolerance of line currents, respectively. Finally, the proposed scheme is completed by combining the foregoing two elements with a predictive direct power control (PDPC). In order to verify the feasibility and validity of the proposed SOGI-VFPDPC, the scenarios of unbalanced voltage dip, higher harmonic distortion and grid frequency deviation are investigated in simulation and experimental studies. The corresponding results demonstrate that the proposed strategy ensures a balanced sinusoidal line current operation with excellent steady-state and transient behaviors under general grid conditions.

A Harmonic Suppressed Design of Size Reduced Ring-Hybrid Using Folded Line Structure (소형화 및 고조파 특성이 개선된 접힌 구조의 링-하이브리드의 설계)

  • Lee Hong-Seop;Lee Chul-Heui;Hwang Hee-Yong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.9 s.112
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    • pp.845-851
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    • 2006
  • Folded lines are applied to design a compact microstrip ring hybrid. Using the proposed structure we achieve both significant size reduction and good harmonic suppression with the same results of conventional ring hybrid at 2.41 GHz. Including the third harmonic frequency, up to 11 GHz band harmonics are suppressed to -20 dB. The size of the proposed ring-hybrid is reduced to one forth of the conventional ring hybrid. The measured frequency responses agree well with simulated ones.

Optimal Switching Pattern of Voltage Source Inverter (전압원인버어터의 최적스위칭패턴)

  • 정필선;정동화;이윤종
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.12 no.4
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    • pp.386-398
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    • 1987
  • This paper is proposed the Suboptimal PAWM(Pulse Amplitude Width Modulation) for minimize harmonic effects generated by switching operation of PWM Inverter. This strategy determine one switching pattern at a fixed point(fundamental) voltage u1=1.2) which THD(Total Harmonic Distortion) are minimized in the suboptimal PWM strategy, and controls only frequency in the inverter while voltage control is carried out by DC Chopper in the DC Link. This strategy is applied at VSD(Variable Speed Drive) of Three phase induction moter, and acoustic noise of motor, line to line voltage and current of inverter, current harmonic spectrum was estimated and also compared with other switching strategy. From the results, the validity of this strategy can be verified.

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