• Korean Journal of Agricultural Science
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• v.47 no.4
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• pp.1029-1037
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• 2020

The machine learning algorithm has been widely used in water-related fields such as water resources, water management, hydrology, atmospheric science, water quality, water level prediction, weather forecasting, water discharge prediction, water quality forecasting, etc. However, water quality prediction studies based on the machine learning algorithm are limited compared to other water-related applications because of the limited water quality data. Most of the previous water quality prediction studies have predicted monthly water quality, which is useful information but not enough from a practical aspect. In this study, we predicted the dissolved oxygen (DO) using recurrent neural network with long short-term memory model recurrent neural network long-short term memory (RNN-LSTM) algorithms with hourly- and daily-datasets. Bugok Bridge in Oncheoncheon, located in Busan, where the data was collected in real time, was selected as the target for the DO prediction. The 10-month (temperature, wind speed, and relative humidity) data were used as time prediction inputs, and the 5-year (temperature, wind speed, relative humidity, and rainfall) data were used as the daily forecast inputs. Missing data were filled by linear interpolation. The prediction model was coded based on TensorFlow, an open-source library developed by Google. The performance of the RNN-LSTM algorithm for the hourly- or daily-based water quality prediction was tested and analyzed. Research results showed that the hourly data for the water quality is useful for machine learning, and the RNN-LSTM algorithm has potential to be used for hourly- or daily-based water quality forecasting.

• The Journal of the Korea Contents Association
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• v.22 no.6
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• pp.56-68
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• 2022

Recently, as the demand for real-time processing increases, studies on a dynamic graph that changes over time has been actively done. There is a connected components processing algorithm as one of the algorithms for analyzing dynamic graphs. GPUs are suitable for large-scale graph calculations due to their high memory bandwidth and computational performance. However, when computing the connected components of a dynamic graph using the GPU, frequent data exchange occurs between the CPU and the GPU during real graph processing due to the limited memory of the GPU. The proposed scheme utilizes the Weighted-Quick-Union algorithm to process large-scale graphs on the GPU. It supports fast connected components computation by applying the size to the connected component label. It computes the connected component by determining the parts to be recalculated and minimizing the data to be transmitted to the GPU. In addition, we propose a processing structure in which the GPU and the CPU execute asynchronously to reduce the data transfer time between GPU and CPU. We show the excellence of the proposed scheme through performance evaluation using real dataset.

• The KIPS Transactions:PartC
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• v.18C no.2
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• pp.89-96
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• 2011

ASR is an excellent program security technique that protects various data memory areas without run-time overhead. ASR hides the addresses of variables from attackers by reordering variables within a data memory area; however, it can be broken by brute force attacks because of a limited data memory space. In this paper, we propose Multiple ASR to overcome the limitation of previous ASR approaches. Multiple ASR separates a data memory area into original and duplicated areas, and compares variables in each memory area to detect an attack. In original and duplicated data memory areas variables are arranged in the opposite order. This makes it impossible to overwrite the same variables in the different data areas in a single attack. Although programs with Multiple ASR show a relatively high run-time overhead due to duplicated execution, programs with many I/O operations such as web servers, a favorite attack target, show 40~50% overhead. In this paper we develop and test a tool that transforms a program into one with Multiple ASR applied.

• Journal of Korea Multimedia Society
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• v.11 no.5
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• pp.651-660
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• 2008

Flash memory is widely used in embedded systems because of its benefits such as non-volatile, shock resistant, and low power consumption. However, NAND flash memory suffers from out-place-update, limited erase cycles, and page based read/write operations. To solve these problems, YAFFS and RFFS, the flash memory file systems, are proposed. However YAFFS takes long time to mount the file system, because all the files are scattered all around flash memory. Thus YAFFS needs to fully scan the flash memory. To provide fast mounting, RFFS has been proposed. It stores all the block information, the addresses of block information and meta data to use them at mounting time. However additional operations for the meta data management are decreasing the performance of the system. This paper presents a new NAND flash file system called ERFFS (Efficient and Reliable Flash File System) which provides fast mounting and recovery with minimum mata data management. Based on the experimental results, ERFFS reduces the flash mount/recovery time and the file system overhead.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.2
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• pp.159-164
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• 2016

A wireless communication system is required to be implemented with the low power circuits because it uses a battery having a limited energy. Therefore, the current mode circuit has been studied because it consumes constant power regardless of the frequency change. However, the clock-feedthrough problem is happened by leak of stored energy in memory operation. In this paper, we suggest the current memory circuit to minimize the clock-feedthrough problem and introduce a technique for ultra low power operation by inducing dynamic voltage scaling. The current memory circuit was designed with BSIM3 model of $0.35{\mu}m$ process and was operated in the near-threshold region. From the simulation result, the clock-feedthrough could be minimized when designing the memory MOS Width of $2{\mu}m$, the switch MOS Width of $0.3{\mu}m$ and dummy MOS Width of $13{\mu}m$ in 1MHz switching operation. The power consumption was calculated with $3.7{\mu}W$ at the supply voltage of 1.2 V, near-threshold voltage.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.1
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• pp.71-76
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• 2022

Buffer cache bridges the performance gap between memory and storage, but its effectiveness is limited due to periodic flush, performed to prevent data loss in smartphones. This paper shows that selective flushing technique with small persistent memory can reduce the flushing overhead of smartphone buffer cache significantly. This is due to our I/O analysis of smartphone applications in that a certain hot data account for most of file writes, while a large proportion of file data incurs single-writes. The proposed selective flushing policy performs flushing to persistent memory for frequently updated data, and storage flushing is performed only for single-write data. This eliminates storage write traffic and also improves the space efficiency of persistent memory. Simulations with popular smartphone application I/O traces show that the proposed policy reduces write traffic to storage by 24.8% on average and up to 37.8%.

• Korean Journal of Cognitive Science
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• v.16 no.3
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• pp.155-174
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• 2005

Oh and Kim (2004) and Woodman and Lurk (2004) demonstrated that spatial working memory (SWM) load Interfered concurrent visual search and that search process also impaired the maintenance of spatial information implying that visual search and SWM task both require access to the same limited-capacity mechanism. Two obvious possibilities have been suggested about what this shared limited-capacity mechanism is: common demand for attention to the locations where the items f9r the two tasks were presented (spatial attention load hypothesis), and common use of working memory to maintain a record of locations have been processed(SWM load hypothesis). To test these two hypothetical explanations, Experiment 1 replicated the mutual interference between visual search and SWM task in spite of difference of procedure with preceding researches; possible areas where the items for two tasks were presented were not separated. In Experiment 2, we presented the items for visual search either in the same quadrants where the items for SWM task had appeared (same-location rendition) or in the different quadrants (different-location condition). As a result, search efficiency was more impaired in the different-location condition than in the same-location condition. The memory accuracy was worse in the different-location rendition than in the same-location rendition. Overall results of study indicate that the mutual interference between SWM and visual search might be related to the overload of spatial attention, but not to that of SWM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

• Journal of the Korea Society of Computer and Information
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• v.16 no.8
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• pp.19-27
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• 2011

Access control that has been previously performed mainly on safety, and thus not much effort has been done to consider access control in terms of efficiency. This paper proposes a method for an efficient and secure query processing of XML data streams, such as a personal digital assistant and a portable terminal, at the client side with limited resources. Specifically, this paper proposes an access control processing that possesses a small overhead for attaining a secure result with limited memory and a method to enhance the performance, finding the parts capable of optimizing each processing step for offsetting the overhead caused by the addition of access control processing. The superiority of the new method is analyzed through an experiments.

• Journal of Digital Contents Society
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• v.18 no.6
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• pp.1165-1173
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• 2017

Deep learning method, which is one of the most famous machine learning algorithms, has proven its applicability in various applications and is widely used in digital signal processing. However, it is difficult to apply deep learning technology to IoT devices with limited CPU performance and memory capacity, because a large number of training samples requires a lot of memory and computation time. In particular, if the Arduino with a very small memory capacity of 2K to 8K, is used, there are many limitations in implementing the algorithm. In this paper, we propose a method to optimize the ELM algorithm, which is proved to be accurate and efficient in various fields, on Arduino board. Experiments have shown that multi-class learning is possible up to 15-dimensional data on Arduino UNO with memory capacity of 2KB and possible up to 42-dimensional data on Arduino MEGA with memory capacity of 8KB. To evaluate the experiment, we proved the effectiveness of the proposed algorithm using the data sets generated using gaussian mixture modeling and the public UCI data sets.