• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.8
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• pp.72-80
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• 1993

We fabricated 0.3um gate length inverse-T gate MOS(ITMOS) and conventional lightly doped drain oxide spacer MOS(LDDMOS), and studied electrical characteristics for comparison. Threshold voltage of 0.3um gate length device was 0.58 V for ITMOS and 0.6V for LDDMOS. Measured subthreshold characteristics showed a slope of 85mV/decades for both ITLDD and LDDMOS. Maximum transconductance at V S1ds T=V S1gs T=3.3V was 180mS/mm for ITMOS and 163mS/mm for LDDMOS respectively. GIDL current was observed to be 0.1pA/um for ITOMS and 0.8pA/um for LDDMOS. Substrate current of ITMOS as a function of drain current was found to be reduced by a foactor of 2.5 compared with that of LDDMOS.

• Journal of Semiconductor Engineering
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• v.3 no.2
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• pp.161-167
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• 2022

Electrical characteristics of LDMOS power device with LDD(Lightly Doped Drain) structure is studied with variation of the region of channel and LDD. The channel in LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of CMOS inverter. Two-dimensional TCAD MEDICI simulation is used to study hot-carrier effect, on-resistance Ron, breakdown voltage, and transient switching characteristic. The voltage-transfer characteristics and on-off switching properties are studied as a function of the channel length and doping levels. The digital logic levels of the output and input voltages are analyzed from the transfer curves and circuit operation. Study indicates that drain current significantly depends on the channel length rather than the LDD region, while the switching transient time is almost independent of the channel length. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.140-140
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• 2010

Non-mass analyzed ion shower doping (ISD) technique with a bucket-type ion source or mass-analyzed ion implantation with a ribbon beam-type has been used for source/drain doping, for LDD (lightly-doped-drain) formation, and for channel doping in fabrication of low-temperature poly-Si thin-film transistors (LTPS-TFT's). We reported an abnormal activation behavior in boron doped poly-Si where reverse annealing, the loss of electrically active boron concentration, was found in the temperature ranges between $400^{\circ}C$ and $650^{\circ}C$ using isochronal furnace annealing. We also reported reverse annealing behavior of sequential lateral solidification (SLS) poly-Si using isothermal rapid thermal annealing (RTA). We report here the importance of implantation conditions on the dopant activation. Through-doping conditions with higher energies and doses were intentionally chosen to understand reverse annealing behavior. We observed that the implantation condition plays a critical role on dopant activation. We found a certain implantation condition with which the sheet resistance is not changed at all upon activation annealing.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.311-316
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• 2001

The technology for characteristic analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high-integrated device by computer simulation and fabricate the device having such characteristics became one of very important subjects. At devices become smaller from submicron to nanometer, we have investigated MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane, and also newEPI MOSFET for improved structure to weak point of LDD structure by TCAD(Technology Computer Aided Design) to develop optimum device structure. We analyzed and compared the EPI device characteristics such as impart ionization, electric field and I-V curve with those of lightly-doped drain(LDD) MOSFET. Also, we presented that TCAD simulator is suitable for device simulation and the scaling theory is suitable at nano structure device.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.11
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• pp.1227-1232
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• 2014

This paper relates 10% shrink from $0.13{\mu}m$ design for core devices as well as input and output (I/O) devices different from previous poly length shrink size only. We analyzed body effect with different channel length and doping profile simulation. After fixing the gate oxide module process, LDD implant conditions were optimized such as decoupled plasma nitridation of gate oxide, TEOS oxide $100{\AA}$ before LDD implant and 22o tilt-angle(45o twist-angle) LDD implant respectively to match the spice DC parameters of pre-shrink and finally matched them within 5%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.490-493
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• 2000

The technology for characteristics analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high integrated device by computer simulation and to fabricate the device having such characteristics became one of very important subjects. As devices become smaller to submicron, we have investigated MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane by TCAD(Technology Computer Aided Design) to develop optimum device structure. We compared and analyzed the characteristics of such device structure, i.e., impact ionization, electric field and I-V characteristics curve with lightly-doped drain(LDD) MOSFET. Also, we presented that TCAD simulator is suitable for device simulation.

• ETRI Journal
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• v.14 no.1
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• pp.52-65
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• 1992

전자선 직접묘사 (E-beam direct writing lithography) 방법을 이용하여 $0.2\mum$ 과 $0.3\mum$ 의 게이트길이를 가지는 NMOS 트랜지스터를 제작하였다. 게이트만 전자선 직접묘사 방법으로 정의하고 나머지는 optical stepper를 이용하는 Mix & Match 방식을 사용하였다. 게이트산화막의 두께는 최소 6nm까지 성장시켰으며, 트랜지스터구조로서는 lightly-doped drain(LDD) 구조를 채택하였다. 짧은 채널효과 및 punch through를 줄이기 위한 방안으로 채널에 깊이 붕소이온을 주입하는 방법과 well을 고농도로 도핑하는 방법 및 소스와 드레인에 $p^-$halo를 이온주입하는 enhanced lightly-doped drain(ELDD) 방법을 적용하였으며, 제작후 성능을 각각 비교하였다. 제작된 $0.2\mum$의 게이트길이를 가지는 소자에서는 문턱전압과 subthreshold기울기는 각각 0.69V 및 88mV/dec. 이었으며, Vds=3.3V에서 측정한 포화 transconductance와 포화 드레인전류는 각각 200mS/mm, 0.6mA/$\mum$이었다. $0.3\mum$소자에서는 문턱전압과 subthreshold 기울기는 각각 0.72V 및 82mV/dec. 이었으며, Vds=3.3V에서 측정한 포화 transconductance는 184mS/mm이었다. 이러한 결과는 전원전압이 3.3V일 때 실제 ULSI에 적용가능함을 알 수 있다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.342-343
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• 2012

We studied the Drain-Induced-Barrier-Lowering (DIBL) effect by different drain engineering. One other drain engineering is symmetric source-drain n-channel MOSFETs (SSD NMOSs), the other drain engineering is asymmetric source-drain n-channel MOSFETs (ASD NMOSs). Devices were fabricated using state of art 40 nm dynamic-random-access-memory (DRAM) technology. These devices have different modes which are deep drain junction mode in SSD NMOSs and shallow drain junction mode in ASD NMOSs. The shallow drain junction mode means that drain is only Lightly-Doped-Drain (LDD). The deep drain junction mode means that drain have same process with source. The threshold voltage gap between low drain voltage ($V_D$=0.05V) and high drain voltage ($V_D$=3V) is 0.088V in shallow drain junction mode and 0.615V in deep drain junction mode at $0.16{\mu}m$ of gate length. The DIBL coefficients are 26.5 mV/V in shallow drain junction mode and 205.7 mV/V in deep drain junction mode. These experimental results present that DIBL effect is higher in deep drain junction mode than shallow drain junction mode. These results are caused that ASD NMOSs have low drain doping level and low lateral electric field.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.321-324
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• 2001

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased packing density. This paper has compared Micro-Tec with ISE-TCAD. This paper investigates LDD MOSFET using two simulators. Bias condition is applied to the devices with gate lengths 180nm. We have presented MOSF ET's characteristics such as I-V characteristic, electric field. and compared with Micro-Tec and ISE-TCAD.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.96-106
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• 1996

One of the major problems for poly-Si TFTs is the large off state leakage current. LDD (lightly doped drain) and offset gated structures have been employed in order to reduce the leakage current. However, these structures also redcue the oN current significantly due to the extra series resistance caussed by the LDD or offset region. It is desirable to have a device which would have the properties of the offset gated structure in the OFF state, while behaving like a fully gated device in the oN state. Therefore, we propose a new thin film transistor with pnp junction gate which reduce the leakage curretn during the OFF state without sacrificing the ON current during the ON state.