• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.91-101
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• 2012

DNA watermarking have been interested for both the security of private genetic information or huge DNA storage information and the copyright protection of GMO. Multimedia watermarking has been mainly designed on the basis of frequency domain, such as DCT, DWT, FMT, and so on, for the robustness and invisibility. But a frequency domain watermarking for coding DNA sequence has a considerable constraint for embedding the watermark because transform and inverse transform must be performed without completely changing the amino acid sequence. This paper presents a coding sequence watermarking on lifting based DWT domain and brings up the availability of frequency domain watermarking for DNA sequence. From experimental results, we verified that the proposed scheme has the robustness to until a combination of 10% point mutations, 5% insertion and deletion mutations and also the amino preservation and the security.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.97-104
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• 2004

This paper proposes an efficient VLSI architecture of 9-7/5-3 Lifting DWT filters that is used by lossy or lossless compression of JPEG2000. The proposed architecture uses only internal line memories to compute Lifting-DWT operations and its PE(Processing Element) has critical path with 1 multiplier and 1 adder. To reduce the number of PE, we make the vertical filter that is responsible for the column operations of the first level perform both the row and column operations of the second and following levels. As a result, the architecture has smaller hardware cost compared to that of other architectures. It was modeled in RTL level using VHDL and implemented on Altera APEX 20K FPGA.

• Journal of Broadcast Engineering
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• v.6 no.1
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• pp.32-40
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• 2001

In this paper, we propose a DWT (discrete Wavelet Transform) based watermarking method, which can be conveniently Integrated In the up-coming JPEG2770 baseline system. Although Conventional DWT based watermarking techniques insert watermark signal Into wavelet coefficients after the transform, our proposed method embeds a watermark into wavelet coefficients obtained from the ongoing process of lifting for DWT. The proposed method allows us to selectively determine frequency characteristics of the coefficients where the watermark is embedded. so that the Inserted watermark cannot be removed or altered even when the filter-bank for DWT is known. Through the simulation, we show that the proposed method is more secure and more robust against various attacks than conventional DWT barred watermarking techniques.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.993-1000
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• 2012

In this research, we proposed an efficient VLSI architecture of the lifting-based 2D DWT (Discrete Wavelet Transform) filter with 100% hardware utilization. The (9,7) filter structure has been applied and extendable to the filter length. We proposed a new block-based scheduling that computes the DWT for the lower levels on an "as-early-as-possible" basis, which means that the calculation for the lower level will start as soon as the data is ready. Since the proposed 2D DWT computes the outputs of all levels by one row-based scan, the intermediate results for other resolution levels should be kept in storage such as the Data Format Converter (DFC) and the Delay Control Unit (DCU) until they are used. When the size of input image is $N{\times}N$ and m is the filter length, the required storage for the proposed architecture is about 2mN. Since the proposed architecture processes the 2D DWT in horizontal and vertical directions at the same time with 4 input data, the total period for 2D DWT is $N^2(1-2^{-2J})/3$.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.515-518
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• 2000

디지털 워터마킹(Digital Watermarking)은 디지털 미디어 창작물에 대해 불법적인 사용과 인위적인 조작으로부터 소유권과 저작권을 보호하기 위하여 입증 가능한 정보(워터마크)를 사람이 인지하지 못하도록 삽입하는 기술이다. 본 논문에서는 JPEG 2000에서 지원하는 Daubechies 9/7 필터를 이용한 lifting 기반의 DWT(Discrete Wavelet Transform) 중간에 임의의 파라메터를 추가한 lifting 단계를 구성하여 이 부분에 워터마크를 삽입한 후, 다양한 신호처리 왜곡을 가하여 제안한 방법의 성능을 평가하였다. 실험은 8-bit 512×512크기의 영상을 사용하였으며, 무작위로 발생시킨 1과-1을 워터마크 신호로 하여 DWT 시 추가한 lifting 단계에서의 임의의 파라메터 값과 워터마크를 삽입할 각 웨이블릿 변환의 해상도 레벨을 조절해 가면서 선택한 웨이블릿 계수값에 무작위로 발생시킨 워터마크 신호를 삽입하였다. 실험 결과 영상의 일반적인 변형(압축, 필터링 등)에 대해서 제안한 방법의 워터마킹 기법의 성능이 전반적으로 강인함을 확인하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.157-165
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• 2013

In this paper, efficient digit-serial VLSI architecture for 1D (9,7) lifting-based discrete wavelet transform (DWT) filter has been proposed. The proposed architecture computes the DWT in digit basis, so that the required hardware is reduced. Also, the multiplication is replaced with the shift and add operation to minimize the hardware requirement. Bit allocation for input, output, and the internal data has been determined by analyzing the PSNR. We have carefully designed the data feedback latency not to degrade the performance in the recursive folded scheduling. The proposed digit-serial architecture requires small amount of hardware but achieve 100% of hardware utilization, so we try to optimize the tradeoffs between the hardware cost and the performance. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a DongbuHitek $0.18{\mu}m$ STD cell library. The maximum operating frequency is 330MHz with 3,770 gates in equivalent two input NAND gates.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.687-688
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• 2006

This paper presents implementation of the lifting based DWT processor interface which the process of JPEG2000. The proposed architecture uses Excalibur device produced Altera. This study describes CIS(CMOS Image Sensor), DMA(Direct Memory Access) and DWT control logic

• Journal of Korea Multimedia Society
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• v.15 no.1
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• pp.81-86
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• 2012

This paper presents a VLSI design for lifting-based discrete wavelet transform (DWT) 9/7 filter using multiplierless multiple constant multiplication (MCM) architecture. This proposed design is based on the lifting scheme using pattern search for folded architecture. Shift-add operation is adopted to optimize the multiplication process. The conventional serial operations of the lifting data flow can be optimized into parallel ones by employing paralleling and pipelining techniques. This optimized design has simple hardware architecture and requires less computation without performance degradation. Furthermore, hardware utilization reaches 100%, and the number of registers required is significantly reduced. To compare our work with previous methods, we implemented the architecture using Verilog HDL. We also executed simulation based on the logic synthesis using $0.18{\mu}m$ CMOS standard cells. The proposed architecture shows hardware reduction of up to 60.1% and 44.1% respectively at 200 MHz clock compared to previous works. This implementation results indicate that the proposed design performs efficiently in hardware cost, area, and power consumption.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.943-949
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• 2010

This paper presents some improvements on VLSI implementation of lifting-based 9/7 wavelet transform by optimization hardware multiplication. The proposed solution requires less logic area and power consumption without performance loss compared to previous wavelet filter structure based on lifting scheme. This paper proposes a better approach to the hardware implementation using Lefevre algorithm based on extensions of Pattern search methods. To compare the proposed structure to the previous solutions on full multiplier blocks, we implemented them using Verilog HDL. For a hardware implementation of the two solutions, the logical synthesis on 0.18 um standard cells technology show that area, maximum delay and power consumption of the proposed architecture can be reduced up to 51%, 43% and 30%, respectively, compared to previous solutions for a 200 MHz target clock frequency. Our evaluation show that when design VLSI chip of lifting-based 9/7 wavelet filter, our solution is better suited for standard-cell application-specific integrated circuits than prior works on complete multiplier blocks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.75-84
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• 2004

In this paper, we proposed an efficient hardware architecture of line-based lifting algorithm for Motion JPEG2000. We proposed a new architecture of a lifting-based filtering cell which has an optimized and simplified structure. It was implemented in a hardware accommodating both (9,7) and (5,4) filter. Since the output rate is linearly proportional to the input rate, one can obtain the high throughput through parallel operation simply by adding the hardware units. It was implemented into both of ASIC and FPGA The 0.35${\mu}{\textrm}{m}$ CMOS library from Samsung was used for ASIC and Altera was the target for FRGA. In ASIC, the proposed architecture used 41,592 gates for the lifting arithmetic and 128 Kbit memory. For FPGA it used 6,520 LEs(Logic Elements) and 128 ESBs(Embedded System Blocks). The implementations were stably operated in the clock frequency of 128MHz and 52MHz, respectively.