• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.410-413
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• 2001

In this paper, we present results of this that design of the multi-layer VCO(Voltage Controlled Oscillator), which is composed of the resonation circuit and the oscillation circuit, using EM simulator and nonlinear RF circuit simulator. EM simulator is used for acquiring EM(Electromagnetic) characteristics of conductor pattern as well as designing multi-layer VCO, Acquired EM characteristics of the circuit pattern was used like real components at nonlinear RF circuit simulator. Finally VCO is simulated at nonlinear RF circuit simulator. The material for the circuit pattern was Ag and the dielectric was DuPont #9599, which is applied for L TCC process. The structure is constructed with 4 conducting layer. Simulated results showed that the output level was about 1[dBm], the phase noise was 102 [dBc/Hz] at 30[kHz] offset frequency, the harmonics -8dBc, and the control voltage sensitivity of 30[MHz/V] with a DC current consumption of l0[mA]

• 대한전기학회논문지
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• 제43권3호
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• pp.504-514
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• 1994

Combinational automatic test pattern generators (CATPG) have already been commercialized because their algorithms are well known and practical, while sequential automatic test pattern generators(SATPG) have been regarded as impractical because they are computationally complex. A technique to use CATPG instead of SATPG for test generation of sequential circuits is proposed. Redesign of seauential circuits such as Level Sensitive Scan Design (LSSD) is inevitable to use CATPG. Various partial scan techniques has been proposed to avoid full scan such as LSSD. It ha sbeen reported that SATPG is required to use partial scan techniques. We propose a technique to use CATPG for a new partial scan technique, and propose a new CATPG algorithm for the partially scanned circuits. The partial scan technique can be another choice of design for testability because it is computationally advantageous.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.410-413
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• 2001

In this paper, we present results of this that design of the multi-layer VCO(Voltage Controlled Oscillator), which is composed of the resonation circuit and the oscillation circuit, using EM simulator and nonlinear RF circuit simulator. EM simulator is used for acquiring EM(Electromagnetic) characteristics of conductor pattern as well as designing multi-layer VCO, Acquired EM characteristics of the circuit pattern was used like real components at nonlinear RF circuit simulator. Finally VCO is simulated at nonlinear RF circuit simulator. The material for the circuit pattern was Ag and the dielectric was Dupont ＃9599, which is applied for LTCC process. The structure is constructed with 4 conducting layer. Simulated results showed that the output level was about 1[dBm], the phase noise was 102 [dBc/Hz] at 30[kHz] offset frequency, the harmonics -8dBc, and the control voltage sensitivity of 30[MHz/V] with a DC current consumption of 10[mA].

• 패션비즈니스
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• 제18권5호
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• pp.144-158
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• 2014

National Competency Standards(NCS) is to systemize the competency that is necessary for performing duties in industrial fields and to utilize synthetically duty, vocational education training, and qualification at the national level. The purpose of this study is to analyze the process of NCS development and verification, which systemizes competency units and competency unit elements through the analysis of duty in pattern field. It is to cultivate competent people to be able to promote the development of pattern industry ultimately through being a complementary to educational circles and industry then to give them practical knowledge that is demanded in the field. Furthermore, it is to be utilized as a fundamental data for reforming the system of duty competency evaluation so as to manage personnel career systematically and to improve their competency. Focus Group Interview(FGI) was adapted as the method of this study, which was proceeded 3 times, and validity of the drawn result is verified through expert questionnaire survey. Research result, which is competency units, is 10 as follows; Fit trend analysis, Analysis of sample garment Specification sheet, Pattern making for sample garment, Pattern making for manufacturing garment, Creation of sewing specification, Instruction of manufacturing technique, Sample garment Inspection for quality control, Grading, Calculation of the required material quantities, Quality control.

• 한국인터넷방송통신학회논문지
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• 제9권3호
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• pp.217-224
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• 2009

기존의 교육용 소형 다관절로봇은 펌웨어를 이용하여 개발해왔다. 이런 시스템일 경우 단순동작만 수행할 수 있기 때문에 교육용으로 활용가치가 떨어진다. 그러나 교육용 소형 다관절로봇에 RTOS를 적용하면 다양한 동작의 수행이 가능하다. RTOS를 적용하면 시스템의 효율이 높아지지만 SW 복잡도가 높아져 교육용으로 사용하기 어려운 문제가 있다. 이런 문제를 해결하기 위해서 본 논문에서는 디자인 패턴과 리팩토링을 적용한다. 디자인 패턴과 리팩토링을 적용하여 RTOS를 설계하면 이미 알려진 패턴의 개념이 사용되기 때문에 RTOS의 전문 개발자가 아니어도 이해하기 쉬어진다. 뿐만 아니라 설계가 문서화되기 때문에 기존의 RTOS를 이용하여 새로운 시스템에 알맞은 RTOS로 변경이 용이해 진다. 그래서 본 논문에서는 디자인패턴을 사용하여 RTOS를 설계하고 RTOS 코드에 리팩토링을 적용하였다.

• 대한전자공학회논문지SD
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• 제38권3호
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• pp.185-197
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• 2001

최근 VHDL 코딩 및 합성방법에 의한 설계가 널리 사용되고 있다. 집적도가 증가함에 따라 VHDL에 의한 설계 또한 그 분량이 증가하여 많은 코딩오류가 발생하고 있으며, 이를 검색하는데 많은 시간과 노력이 소요되고 있다. 본 논문에서는 VHDL 행위-레벨 설계를 대상으로 코딩오류를 검색하는 방법을 제안하였다. 그 방법에 있어서는 검색패턴을 생성하여 오류가 없는 응답과 설계의 응답을 비교함으로써 설계오류를 찾는 방법을 택하였다. 따라서 본 논문에서는 코딩오류를 검색하기 위한 검색패턴을 생성하는 알고리듬을 제안하였다. 검색패턴 생성은 각 코드에 대해 수행하며, 할당오류와 조건오류를 구분하여 수행하였다. 패턴생성을 위해 VHDL 코드를 CDFG로 변환하여 사용하며, CDFG상의 경로를 탐색하여 패턴생성에 필요한 정보를 추출한다. 경로탐색은 오류가 발생하였다고 가정한 지점으로부터 역방향 탐색과 정방향 탐색을 수행하여 패턴을 생성한다. 제안한 알고리듬은 C-언어로 구현하였다. 펜티엄-Ⅱ 400MHz의 환경에서 여러 가지 VHDL 행위-레벨 설계를 대상으로 제안한 알고리듬을 적용하였다. 그 결과, 고려한 모든 설계의 모든 코드에 대한 검색패턴을 생성할 수 있었으며, 가정한 모든 오류를 검색할 수 있었다. 검색패턴 생성에 소요되는 시간은 고려한 모든 대상 설계에서 1초 미만의 CPU 시간을 보여 속도면에서도 매우 우수함을 나타내었다. 따라서 본 논문에서 제안한 검색방법은 VHDL에 의한 설계에서 설계검증에 필요한 시간과 노력을 상당히 감소시킬 것으로 기대된다.

• 한국컴퓨터산업학회논문지
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• 제5권4호
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• pp.461-470
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• 2004

본 연구는 지하수 관정 인터페이스를 객체지향 기반으로 설계하였다. 복합적 형태의 현실 세계의 지리 객체를 위한 지리 데이터베이스 구현을 위하여 추상화 단계에서 분석 유형에 대하여 연구하였다. 응용영역에 적합한 유형을 규정하고 객체지향 방법론에 기반 한 UML을 이용하여 분석유형을 설계함으로서 대규모 개방 시스템을 개발하고 배포할 수 있는 컴포넌트의 재사용 성을 증가시키는데 기여하고자 한다.

• 반도체디스플레이기술학회지
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• 제20권3호
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• pp.45-50
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• 2021

The adjustment of lens magnification can make the degree of precision in pattern measurement be improved, but several problems such as high cost, smaller field of view and stage error accumulation are followed. In this paper, a method for precisely measuring patterns is proposed based on gradient transition vector, in order to solve these problems. The performance of our method is evaluated using pattern images with several directions. Also, it is compared with previous methods based on edge and gray-level moment. It is judged that the proposed method outperforms consistent pattern width results, and so could be applied to automation processes for measurement and inspection of precise and complexed patterns in IT, BT industry products.

• 복식문화연구
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• 제23권4호
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• pp.569-580
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• 2015

The recent fashion market failed to satisfy the needs of female customers in their 30s who are demanding a slim jacket that makes the wearer look young and slim. Accordingly, the slim-fit jackets of domestic brands targeting the women in their 30s were collected to conduct look and movement fitting evaluations based on the standard somatotype, and a slim-fit tailored jacket prototype was developed based on the present findings. This research aims to increase the satisfaction level of the slim-fit jacket customers reflecting a variety of somatotypes of women in their 30s. The research process was developing jacket patterns fully reflecting the properties in terms of extra space and design lines for different somatotypes of women in their 30s based on the jacket pattern formulated through the advanced research, and then suggesting pattern design methods for the different somatotypes. In this sense, this research attempted to identify the problems concerning the slim-fit tailored jacket fitting for different somatotypes of women in their 30s. The main aim was to suggest ways to improve the customers' satisfaction level regarding the fit, and enable the manufacturers to produce a well-fitting jacket reflecting the peculiarities of each somatotype.

• 한국실내디자인학회논문집
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• 제21권6호
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• pp.233-242
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• 2012

The purpose of this study is to analyze the pattern of tenant layout for selected cases of five different Urban Entertainment Center(UEC) in Seoul. This research deals with the process of gaining tenant layout pattern of 40 different types. It is composed of three combination unit with tenants of the same or different consumption mode, which is divided into four different functions of retail, entertainment, dining, and service. Then, every tenant of research cases is classified as one of the fabric type, and the data is analyzed to gain its frequency rate with SPSS 14.0 program. The following is the overall explanation of the result for this research. The frequency of tenant layout pattern between the same consumption mode shows the high rate when compared to the other patterns with different consumption mode. For example, the frequency rate of tenant layout pattern which retail and dining consumption mode are placed side by side like RRR and DDD is high. Interestingly, the frequency rate of RRR type of tenant layout pattern that sells the similar products shows especially high level. It can provide the effective environment for shoppers to compare retail goods in many different stores as producing synergic effects when they are located near each other, so this strategy should be considered when planning tenants in UEC environment. Moreover, in case of dining tenants, when they are clustered together in the UEC environment it can play a role as an anchor tenant. Tenant layout pattern of dining-retail and dining-service consumption mode shows the high frequency rate than other layout pattern with other consumption mode. Besides, entertainment consumption tenants combined with dining or retail tenants show the high frequency rate when compared to the pattern combined with service consumption mode.