• 한국진공학회지
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• 제1권1호
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• pp.176-182
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• 1992

CVD 텅스텐의 응력 및 접합 누설전류 특성을 조사하였다. 응력-연속 어닐링온도 의 그래프는 냉각곡선의 응력이 가열곡선의 그것보다 더 높게 나타나는 이력현상을 보인다. SiH4 환원에 의하여 증착된 텅스텐 막이 수소환원에 의하여 증착된 막보다 전반적으로 내부 응력 뿐만 아니라 열 응력도 더 큰 것으로 나타났으며 전자가 후자에 비해 실리콘 기판과의 부착특성이 불량한 것도 이러한 응력차와 유관한 것으로 생각된다. SiH4 환원에 의하여 형 성된 텅스텐 막은 상온에서 인장 응력 상태에 있으며, 온도가 증가됨에 따라 응력이 감소하 다가 $700^{\circ}C$ 부근에서 압축 응력 상태로 바뀌고, 계속 더 온도가 증가됨에 따라 압축 응력 이 급격히 증가한다. SiH4 환원에 의한 텅스텐 막의 증착 온도가 증가함에 따라 n+/p 접합 의 누설전류가 크게 증가하며, 특히 $400^{\circ}C$로 온도가 증가함에 따라 누설전류의 증가폭이 크게 나타났는데, 이것은 수소환원 반응시와 유사하게 텅스텐의 침투(encroachment)에 의 한 실리콘 소모가 그 원인이다. SiH4/WF6 유속비의 증가에 따라서도 누설전류가 증가하는 데 그 효과는 미소한 것으로 나타났다.

• 전기학회논문지
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• 제62권7호
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• pp.891-897
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• 2013

The power system frequency plays an important role in monitoring and controlling the power system. The frequency can be measured through discrete Fourier transform (DFT) coefficients of its positive fundamental frequency. The accuracy of the frequency estimate is severely affected by noise in the power system signal and the leakage effect of the negative fundamental frequency in DFT. This paper proposes a DFT-based frequency estimation algorithm to cope with the noise as well as the leakage effect. In this algorithm, two suitable digital filters are introduced to reduce efficiently frequency estimate error due to the noise. These filters are designed to use a digital bandpass filter and a second-degree integrator. The effectiveness of the proposed algorithm in reduction of frequency estimate error is verified through simulations on noise, harmonics and frequency deviation.

• ETRI Journal
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• 제13권2호
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• pp.21-27
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• 1991

Effects of annealing on the dielectric properties and microstructures of thin tantalum oxide film(25nm) deposited on p-type Si substrate with rf reactive magnetron sputtering were investigated. The leakage current density was remarkably reduced from $10^-8$ to $10^-12$ A/$\mum^2$at the electric field of 2MV/cm after rapid thermal annealing(RTA) in $O_2$at $1000^{\circ}C$, while little leakage reduction was observed after furnace annealing in $O_2$ at $500^{\circ}C$. The structural changes of thin tantalum oxide film after annealing were examined using high resolution electron microscope(HREM). The results of HREM show that substantial reduction in the leakage current density after the RTA in $O_2$ can be attributed to crystallization and reoxidation of the thin amorphous tantalum oxide film.

• 전력전자학회논문지
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• 제27권5호
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• pp.446-454
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• 2022

This study proposes a carrier-based pulse width modulation (PWM) method for leakage current reduction and neutral point (NP) current control in a three-phase three-level converter, which is a carrier-based PWM version of the previously proposed low-frequency common mode voltage PWM. Three groups of space vectors with the same common mode voltage are used. When the averaged NP current needs to be positive or negative, the specific groups are employed to produce low-frequency common mode voltages. The validity of the proposed PWM method is verified through experiments.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

• 한국전기전자재료학회논문지
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• 제11권10호
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• pp.918-923
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• 1998

Poly-silicon thin film transistors were fabricated on quartz substrates by high temperature processes. Electrical characteristics were measured and compared for 3 transistor structures of Standard Inverted Gate(SIG), Lightly Doped Drain(LDD), and Dual Gate(DG). Leakage currents of DG and LDD TFT's were smaller that od SIG transistor, while ON-current of LDD transistor is much smaller than that of SIG and DG transistors. Temperature dependence of the leakage currents showed that SIG and DG TFT's had thermal generation current at small drian bias and Frenkel-Poole emission current at hight gate and drain biases, respectively. In case of LDD transistor, thermal generation was the dominant mechanism of leakage current at all bias conditions. It was found that the leakage current was closely related to the reduction of the electric field in the drain depletion region.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1250-1252
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• 1993

Enhancement mode n-channel TFT leakage current(off current : $V_G<0$) that is little agreement on the conduction mechanism is major disadvantage of poly-silicon TFT in practical use, characteristic analysis and model ing. In this paper, new modeling of leakage current is proposed. The activation energy of leakage current, which is dependent on gate voltage, and leakage current dependent on poly silicon thickness are plausibly explained with this model. This model indicate that the reduction of leakage current is attributable to a decrease of maximum laterial electric field strength in the drain depletion region and to the density of trap.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 D
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• pp.1321-1323
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• 1998

We investigated drain leakage current in GaAs power MESFET. The device we studied by 20 simulation has a $1000{\AA}$ thick AlGaAs buffer layer under n-GaAs active layer. The calculation shows that the leakage current through GaAs substrate is significantly reduced by the buffer layer.

• 한국추진공학회:학술대회논문집
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• 한국추진공학회 2008년 영문 학술대회
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• pp.160-167
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• 2008

The effects of squealer rim height on three-dimensional flows and aerodynamic losses downstream of a high-turning turbine rotor blade have been investigated for a typical tip gap-to-chord ratio of h/c=2.0%. The squealer rim height-to-chord ratio is changed to be $h_{st}/c$=0.00(plane tip), 1.37, 2.75, 5.51, and 8.26%. Results show that as $h_{st}/c$ increases, the tip leakage vortex tends to be weakened and the interaction between the tip leakage vortex and the passage vortex becomes less severe. The squealer rim height plays an important role in the reduction of aerodynamic loss when $h_{st}/c{\leq}2.75%$. In the case of $h_{st}/c{\geq}5.51%$, higher squealer rim cannot provide an effective reduction in aerodynamic loss. The aerodynamic loss reduction by increasing $h_{st}/c$ is limited only to the near-tip region within a quarter of the span from the casing wall.

• 전력전자학회논문지
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• 제22권6호
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• pp.469-475
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• 2017

Using impedance matching techniques as a way to increase system power transferability in capacitive wireless power transmission has been widely investigated in conventional studies. However, these techniques tend to increase the circuit volume and thus counterbalance the advantage of the simplicity in the energy link structure. In this paper, a compact circuit topology with one leakage-enhanced transformer is proposed in order to minimize the circuit volume for the capacitive power transfer system. This topology achieves a reactive compensation, and the system quality factor value can be reduced by the turn ratio. As a result, this topology not only reduces the overall system volume but also minimizes the voltage stress of the link capacitor. An optimal design guideline for the leakage-enhanced transformer is also presented. The advantages of the proposed scheme over the conventional method in terms of power efficiency and circuit volume are revealed through an analytic comparison. The feasibility of applying the new topology is also verified by conducting 50 W hardware tests.