• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.881-883
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• 2005

In case is below length 100nm of gate, various kinds problem can be happened with by threshold voltage change of device, occurrence of leakage current by tunneling because thickness of oxide by 1.5nm low scaling is done and doping concentration is increased. SiO$_2$ dielectric substance can not be used for gate insulator because is expected that tunneling current become 1A/cm$^2$ in 1.5nm thickness low. In this paper, devised double gate MOSFET(DGMOSFET) to decrease effect of leakage current by this tunneling. Therefore, could decrease effect of these leakage current in thickness 1nm low of SiO$_2$ dielectric substance. But, very big gate insulator of permittivity should be developed for develop device of nano scale.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.240-248
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• 2009

Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-$\kappa$ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.

• IEIE Transactions on Smart Processing and Computing
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• v.1 no.2
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• pp.117-124
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• 2012

A client collaboration (CC) system is proposed for a user relay system. The proposed scheme focuses on the management of transmit power and leakage interference. In the proposed CC system, edge users transmit signals to the masters considered as user relays. The masters relay the signals of the edge users to the base station using the resource blocks (RBs) that are assigned to the edge users. The leakage interference and power consumption were analyzed in the CC system. In addition, an optimal master location problem was formulated based on the signal-to-leakage-plus-noise ratio (SLNR). Because the optimal master location problem is quite complex, a sub-optimal master location problem was proposed and a closed-form sub-optimal master location was obtained. The edge users generate smaller leakage interference and power consumption in the proposed CC system compared to the system without the CC. The numerical results showed that the edge users generate smaller leakage interference and power consumption in the proposed CC system compared to the system without the CC, and the average throughput increases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.11-19
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.190-194
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• 2017

Present-day solar panels incorporate inverters as their core components. Switching devices driven by specialized power controllers are operated in a transformerless inverter topology. However, some challenges associated with this configuration include the absence of isolation, causing leakage currents to flow through various components toward ground. This inevitably causes power losses, often being also the primary reason for the power inverters' analog equipment failure. In this paper, various aspects of the leakage currents are studied using different circuit analysis methods. The primary objective is to convert the leakage current energy into a usable DC voltage source. The research is focused on harvesting the leakage currents for producing circa 1.1 V, derived from recently developed rectifier circuits, and driving a $200{\Omega}$ load with a power in the milliwatt range. Even though the output voltage level is low, the harvested power could be used for charging small batteries or capacitors, even driving light loads.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.285-291
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• 2013

In this paper, MOS-Capacitor and MOSFET devices with a Low Level Leakage Current of oxide thickness, channel width and length respectively were to investigate the reliability characterizations mechanism of ultra thin gate oxide films. These stress induced leakage current means leakage current caused by stress voltage. The low level leakage current in stress and transient current of thin silicon oxide films during and after low voltage has been studied from strss bias condition respectively. The stress channel currents through an oxide measured during application of constant gate voltage and the transient channel currents through the oxide measured after application of constant gate voltage. The study have been the determination of the physical processes taking place in the oxides during the low level leakage current in stress and transient current by stress bias and the use of the knowledge of the physical processes for driving operation reliability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.37-43
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• 2008

This paper introduces a high-speed low-power self-timed current-mode logic (STCML) that reduces both dynamic and leakage power dissipation. STCML significantly reduces the leakage portion of the power consumption using a pulse-mode control for shorting the virtual ground node. The proposed logic style also minimizes the dynamic portion of the power consumption due to short-circuit current by employing an enhanced self-timing buffer. Comparison results using a 80-nm CMOS technology show that STCML achieves 26 times reduction on leakage power consumption and 27% reduction on dynamic power consumption as compared to the conventional current-mode logic. They also indicate that up to 59% reduction on leakage power consumption compared to differential cascode voltage switch logic (DCVS).

• Proceedings of the Korean Geotechical Society Conference
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• 2005.03a
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• pp.1211-1218
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• 2005

Temperature variation according to space and time on the inner parts of engineering constructions(e.g.: dam, slope) can be a basic information for diagnosing their safety problem. In general, as constructions become superannuated, structural deformation(e.g.: cracks, defects) could be occurred by various factors. Seepage or leakage of water through these cracks or defects in old dams will directly cause temperature anomaly. Groundwater level also can be easily observed by abrupt change of temperature on the level. This study shows that the position of seepage or leakage in dam body can be detected by multi-channel temperature monitoring using thermal line sensor. For this, diverse temperature monitoring experiments for a leakage physical model were performed in the laboratory. In field application of an old dam, temperature variations for water depth and for inner parts of boreholes located at downstream slope were measured. Temperature monitoring results for a long time at the bottom of downstream slope of the dam showed the possibility that temperature monitoring can provide the synthetic information about flowing path and quantity of seepage of leakage in dam body.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.9
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• pp.1231-1240
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• 2020

Water pipes are laid on the ground, making it impossible to visually detect leaks due to aging of pipes, and technology to detect leaks in pipes is mainly used to detect leaks in pipes by detecting leaks. In this paper, two accelerometers were attached to both ends of the constant water piping to calculate the time difference between the acquired data to detect leakage points. The leak test of piping was performed by installing valves at 4.3m, 8.6m, and 12.9m points on piping 17.2m, and changing the development rate of valves to 30% and 70%. Leakage can be detected for pressure drop in piping, which is 30% and 70% open valve. It is very important to detect leakage in the early stage, and it is judged that detection of the initial leak point from the algorithm applied in this paper will be possible.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.238-241
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• 2022

North Korea launched an ICBM and declared Moratorium for the September 19 military talks. The Armed Forces must protect military security for national defense and security. The Ministry of National Defense, which received a hacking attack from North Korea, must protect its military security even more. Recently, the leakage of military data through smartphones is occurring through smartphones. Officers and non-commissioned officers can use smartphones while working. Therefore, smartphone forensics is required to check information leakage of military data from smartphones. In this study, forensic leaks of military data from the Galaxy S20 model of S company. Research integrity verification for securing smartphone forensic evidence, securing metadata, and adopting evidence. This study will contribute to the development of military security and forensic technology.